HT46R71D-1 Holtek Semiconductor, HT46R71D-1 Datasheet - Page 21

• Manufacturer Part Number: HT46R71D-1
• Description: Dual Slope A/D Type MCU
• Manufacturer: Holtek Semiconductor

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The suggested charge pump clock frequency is 20kHz.
The application needs to set the correct value to get the
desired clock frequency. For a 4MHz application, the
CHPCKD bits should be set to the value 11, and for a
2MHz application, the bits should be set to 5.
The REGCEN bit in the CHPRC register is the Regula-
tor/ Charge-pump module enable/disable control bit. If
this bit is disabled, then the regulator will be disabled
and the charge pump will be also be disabled to save
power. When REGCEN = 0, the module will enter the
Power Down Mode ignoring the CHPEN setting. The
ADC and OPA will also be disabled to reduce power.
If REGCEN is set to 1 , the regulator will be enabled. If
CHPEN is enabled, the charge pump will be active and
will use VDD as its input to generate the double voltage
output. This double voltage will be used as the input volt-
age for the regulator. If CHPEN is set to 0 , the charge
pump is disabled and the charge pump output will be
equal to the charge pump input, VDD.
Rev. 1.00
REGCEN CHPEN
Bit No.
0
1
1
3~7
0
1
2
CHPCKD0~
CHPCKD4
X
0
1
REGCEN
BGPQST
CHPEN
Label
Charge
Pump
OFF
OFF
ON
Enable/disable Regulator/Charge-Pump module. (1=enable; 0=disable)
Charge Pump Enable/disable setting. (1=enable; 0=disable)
Note: this bit will be ignore if the REGCEN is disable
Band gap quickly start-up function
0: R short, quickly start
1: R off, normal RC filter mode
Every time when REGCEN change from 0 to 1 (Regulator turn on) This bit should be set
to 0 and then set to 1 to make sure the quickly stable. (the minimum 0 keeping time is
about 2ms now )
The Charge pump clock divider. This 5 bits can form the clock divide by 1~32.
Following the below equation:
Charge Pump clock = (f
VOCHP
2 V
V
V
Pin
DD
DD
DD
Regulator
CHPRC (1FH) Register
OFF
ON
ON
SYS
/16) / (CHPCKD+1)
21
Hi-Impedance
VOREG Pin
It is necessary to take care of the V
age is less than 3.6V, then CHPEN should be set to 1 to
enable the charge pump, otherwise CHPEN should be
set to zero. If the Charge pump is disabled and V
less than 3.6V then the output voltage of the regulator
will not be guaranteed.
ADC - Dual Slope
A Dual Slope A/D converter is implemented in this
microcontroller. The dual slope module includes an Op-
erational Amplifier and a buffer for the amplification of
differential signals, an Integrator and a comparator for
the main dual slope AD converter.
There are 2 special function registers related to this
function known as ADCR and ADCD. The ADCR regis-
ter is the A/D control register, which controls the ADC
block power on/off, the chopper clock on/off, the
charge/discharge control and is also used to read out
the comparator output status. The ADCD register is the
A/D Chopper clock divider register, which defines the
chopper clock to the ADC module.
3.3V
3.3V
Function
Disable
Active
Active
OPA
ADC
The whole module is disable,
OPA/ADC will lose the Power
Use for V
(V
Use for V
(V
DD
DD
>3.6V)
=2.2V~3.6V)
DD
Description
DD
DD
is greater than 3.6V
HT46R71D-1
is less than 3.6V
voltage. If the volt-
May 14, 2007
DD
is