HT46R221 Holtek Semiconductor Inc, HT46R221 Datasheet - Page 12

• Manufacturer Part Number: HT46R221
• Description: 8-Bit A/D Type MCU
• Manufacturer: Holtek Semiconductor Inc

tions
WDT is selected (i.e. CLRWDT times equal 1), any exe-
cution of the CLR WDT instruction will clear the WDT. In
case CLR WDT1 and CLR WDT2 are chosen (i.e.
CLRWDT times equal two), these two instructions must be
executed to clear the WDT; otherwise, the WDT may reset
the chip because of time-out.
If the WDT time-out period is selected f
WDT time-out period ranges from f
tions only clear the last two stages of the WDT.
Power down operation - HALT
The HALT mode is initialized by the HALT instruction
and results in the following...
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a warm reset . After the TO and PD flags are ex-
amined, the reason for chip reset can be determined.
The PD flag is cleared by system power-up or executing
the CLR WDT instruction and is set when executing
the HALT instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the PC and SP; the others keep their original status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by the options. Awakening from an I/O port stim-
ulus, the program will resume execution of the next in-
struction. If it is awakening from an interrupt, two
sequences may happen. If the related interrupt is dis-
abled or the interrupt is enabled but the stack is full, the
program will resume execution at the next instruction. If
the interrupt is enabled and the stack is not full, the regu-
lar interrupt response takes place. If an interrupt request
flag is set to 1 before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.
Once a wake-up event occurs, it takes 1024 t
tem clock period) to resume normal operation. In other
words, a dummy period will be inserted after wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
Rev. 1.10
CLR WDT or CLR WDT1 and CLR WDT2 instruc-
The system oscillator will be turned off but the WDT
oscillator keeps running (if the WDT oscillator is se-
lected).
The contents of the on chip RAM and registers remain
unchanged.
WDT will be cleared and recounted again (if the WDT
clock is from the WDT oscillator).
All of the I/O ports maintain their original status.
The PD flag is set and the TO flag is cleared.
CLR WDT times selection option . If the CLR
s
/2
s
12
/2
~f
12
s
/2
(options), the
13
, since the
SYS
(sys-
12
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset can occur:
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm re -
set that resets only the PC and SP, leaving the other cir-
cuits in their original state. Some registers remain un-
changed during other reset conditions. Most registers
are reset to the initial condition when the reset condi-
tions are met. By examining the PD and TO flags, the
program can distinguish between different chip resets .
Note: u means unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).
The functional unit chip reset status are shown below.
PC
Interrupt
WDT
Timer/Event Counter
Input/Output Ports
SP
TO PD
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
0
u
0
1
1
0
u
1
u
1
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
WDT time-out during normal operation
WDT wake-up HALT
Reset timing chart
RESET Conditions
000H
Disable
Clear. After master reset,
WDT begins counting
Off
Input mode
Points to the top of the stack
HT46R22/HT46C22
October 2, 2002