HT46C65 Holtek Semiconductor, HT46C65 Datasheet
HT46C65
Related parts for HT46C65
HT46C65 Summary of contents
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... RISC architecture microcontroller devices specifically designed for A/D product applications that interface di- rectly to analog signals and which require LCD Inter- face. The mask version HT46C65 is fully pin and functionally compatible with the OTP version HT46R65 device. The advantages of low power consumption, I/O flexibil- ity, timer functions, oscillator options, multi-channel A/D Rev ...
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... Block Diagram Rev. 1.80 HT46R65/HT46C65 2 July 14, 2005 ...
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... Pin Assignment Note: The 52-pin QFP package does not support the charge pump (C type bias) of the LCD. The LCD bias type must select the R type by option. Rev. 1.80 HT46R65/HT46C65 3 July 14, 2005 ...
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... Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil- ity. Rev. 1.80 HT46R65/HT46C65 Description +6.0V Storage Temperature ............................-50°C to 125°C SS +0.3V Operating Temperature...........................-40° ...
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... Input High Voltage (RES) IH2 V Low Voltage Reset Voltage LVR V Low Voltage Detector Voltage LVD I/O Port Segment Logic Output I OL1 Sink Current I/O Port Segment Logic Output I OH1 Source Current Rev. 1.80 HT46R65/HT46C65 Test Conditions Min. V Conditions DD ¾ f =4MHz 2.2 SYS ¾ f =8MHz 3.3 SYS ¾ ...
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... System Start-up Timer Period SST t Low Voltage Width to Reset LVR t Interrupt Pulse Width INT t A/D Clock Period AD t A/D Conversion Time ADC t A/D Sampling Time ADCS Note 1/f SYS SYS Rev. 1.80 HT46R65/HT46C65 Test Conditions Min. V Conditions DD 3V 210 V =0. 350 - =0. -180 5V ¾ ...
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... S12 S11 S10 Note: *12~*0: Program counter bits #12~#0: Instruction code bits Rev. 1.80 HT46R65/HT46C65 After accessing a program memory word to fetch an in- struction code, the value of the PC is incremented by 1. The PC then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip ex- ...
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... Note: *12~*0: Table location bits @7~@0: Table pointer bits Rev. 1.80 HT46R65/HT46C65 Location 008H Location 008H is reserved for the external interrupt service program also. If the INT1 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 008H. ...
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... PD;18H) and I/O control registers (PAC;13H, PBC;15H, PDC;19H). The remaining space before the 40H is re- served for future expanded usage and reading these lo- Rev. 1.80 HT46R65/HT46C65 RAM Mapping cations will get 00H . The space before 40H is overlapping in each bank. The general purpose data memory, addressed from 40H to FFH (Bank0 ...
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... TO is set by a WDT time-out Unused bit, read as 0 Rev. 1.80 HT46R65/HT46C65 Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic opera- tions and provides the following functions: Arithmetic operations (ADD, ADC, SUB, SBC, DAA) Logic operations (AND, OR, XOR, CPL) ...
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... Time base request flag (1=active; 0=inactive) 6 RTF Real time clock request flag (1=active; 0=inactive) Rev. 1.80 HT46R65/HT46C65 sired control sequence, the contents should be saved in advance. External interrupts are triggered edge transition of INT0 or INT1 (ROM code option: high to low, low to high, low to high or high to low), and the related interrupt request flag (EIF0 ...
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... For applications where precise RTC frequencies are essential, these components may be re- quired to provide frequency compensation due to different crystal manufacturing tolerances. Rev. 1.80 HT46R65/HT46C65 register 1 (INTC1) which is located at 1EH in the RAM. EMI, EEI0, EEI1, ET0I, ET1I, ETBI, and ERTI are all used to control the enable/disable status of interrupts ...
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... WDT; otherwise, the WDT may reset the chip due to time-out. Multi-function Timer The HT46R65/HT46C65 provides a multi-function timer for the WDT, time base and RTC but with different time-out periods. The multi-function timer consists of an 8-stage divider and a 7-bit prescaler, with the clock source coming from the WDT OSC or RTC OSC or the instruction clock (i ...
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... The PDF flag is set but the TO flag is cleared. LCD driver is still running (if the WDT OSC or RTC OSC is selected). Rev. 1.80 HT46R65/HT46C65 Time Base The system quits the HALT mode by an external reset, an interrupt, an external falling edge signal on port WDT overflow. An external reset causes device initial- ization, and the WDT overflow performs a warm reset ...
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... WDT starts counting Timer/event Counter Off Input/output Ports Input mode Stack Pointer Points to the top of the stack Rev. 1.80 HT46R65/HT46C65 Reset Circuit Note: * Make the length of the wiring, which is con- nected to the RES pin as short as possible, to avoid noise interference. Reset Timing Chart ...
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... ADCR 0100 0000 0100 0000 ACSR 1--- --00 1--- --00 Note: * stands for warm reset u stands for unchanged x stands for unknown Rev. 1.80 HT46R65/HT46C65 RES Reset RES Reset WDT Time-out (Normal Operation) (HALT) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 ...
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... TMR0H (TMR1H) and TMR0L (TMR1L) regis- ters, respectively. The Timer/Event Counter 1/0 preload Rev. 1.80 HT46R65/HT46C65 register is changed by each writing TMR0H (TMR1H) operations. Reading TMR0H (TMR1H) will latch the contents of TMR0H (TMR1H) and TMR0L (TMR1L) counters to the destination and the lower-order byte buffer, respectively ...
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... T1M1 11= Pulse Width measurement mode (External clock) 00= Unused Rev. 1.80 HT46R65/HT46C65 transient occurs again. In other words, only 1-cycle measurement can be made until the T0ON/T1ON is set. The cycle measurement will re-function as long as it re- ceives further transient pulse. In this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges ...
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... T2 rising edge of instruction MOV A,[m] (m=12H, 14H Rev. 1.80 HT46R65/HT46C65 or 18H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PDC) to control the input/output configuration ...
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... PWM0/PWM1/PWM2/PWM3 signal will appear on PD0/PD1/PD2/PD3 (if PD0/PD1/ PD2/PD3 is operating in output mode). Writing 1 to Rev. 1.80 HT46R65/HT46C65 Input/Output Ports PD0~PD3 data register will enable the PWM output function and writing 0 will force the PD0~PD3 to re- main The I/O functions of PD0/PD1/PD2/PD3 are as shown ...
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... Each modulation cycle has 64 PWM input clock period (6+2) bit PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM Rev. 1.80 HT46R65/HT46C65 register is denoted by DC which is the value of PWM.7~PWM.2. The group 2 is denoted by AC which is the value of PWM.1~PWM.0. ...
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... A/D converter. The bit2~bit0 of the ADCR are used to select an analog input channel. There are a total of eight channels to select. The bit5~bit3 of the ADCR are used Rev. 1.80 HT46R65/HT46C65 to set PB configurations. PB can be an analog input or as digital I/O line decided by these 3 bits. Once a PB line is selected as an analog input, the I/O functions and pull-high resistor of this I/O line are disabled and the A/D converter circuit is powered-on ...
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... Analog Input Channel Selection Register Bit7 Bit6 ADRL (24H ADRH (25H Note: D0~D9 is A/D conversion result data bit LSB~MSB. ADRL (24H), ADRH (25H) Register Rev. 1.80 HT46R65/HT46C65 Function ADCR (26H) Register PB6 PB5 PB4 PB3 PB2 PB6 PB5 PB4 ...
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... ADRL register mov adrl_buffer,a ; save result to user defined memory : : jmp start_conversion ; start next A/D conversion Rev. 1.80 HT46R65/HT46C65 /8 as the A/D clock SYS A/D Conversion Timing 24 July 14, 2005 ...
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... LCD Driver Output The output number of the device LCD driver can option (i.e., 1/2 duty, 1/3 duty or Rev. 1.80 HT46R65/HT46C65 Display Memory 1/4 duty). The bias type LCD driver can be R type or C type. If the R bias type is selected, no external ca- pacitor is required. If the C bias type is selected, a ca- pacitor mounted between C1 and C2 pins is needed ...
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... SEG0~SEG7 and SEG8~SEG15 are together byte optioned as logical output, SEG16~SEG23 are bit individually optioned as logical outputs. LCD Type R Type LCD Bias Type 1/2 bias 1/3 bias If V >V , then V DD LCD MAX V MAX else V connect to V MAX Rev. 1.80 HT46R65/HT46C65 C Type 1/2 bias 1/3 bias > then V connect to V DD, DD LCD MAX 2 LCD else V connect to V1 MAX ...
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... To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. Rev. 1.80 HT46R65/HT46C65 Function RTCC (09H) Register The relationship between V and V ...
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... PD1: level output or PWM1 output PD2: level output or PWM2 output PD3: level output or PWM3 output INT0 or INT1 triggering edge selection: disable; high to low; low to high; low to high or high to low. LCD bias current selection: low/high driving current (for R type only). Rev. 1.80 HT46R65/HT46C65 Options ...
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... VMAX connect to VDD or VLCD or V1 refer to the table. LCD Type R Type LCD bias type 1/2 bias 1/3 bias If V >V , then VMAX connect LCD VMAX else VMAX connect to V Rev. 1.80 HT46R65/HT46C65 C1 0pF 10k 10pF 12k 0pF 10k 25pF 10k 25pF 10k 35pF ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.80 HT46R65/HT46C65 Instruction Description 30 Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV ...
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... Otherwise the original instruction cycle is unchanged. (3) (1) (2) : and (4) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.80 HT46R65/HT46C65 Instruction Description 31 Flag Cycle Affected 2 None (2) 1 ...
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... Affected flag(s) TO PDF ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO PDF Rev. 1.80 HT46R65/HT46C65 ...
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... Operation Stack Program Counter+1 Program Counter Affected flag(s) TO PDF CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO PDF Rev. 1.80 HT46R65/HT46C65 addr ...
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... PDF 0* 0* CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO PDF Rev. 1.80 HT46R65/HT46C65 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO PDF Rev. 1.80 HT46R65/HT46C65 (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C ...
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... Operation Program Counter Affected flag(s) TO PDF MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO PDF Rev. 1.80 HT46R65/HT46C65 Program Counter addr OV Z ...
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... Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO PDF Rev. 1.80 HT46R65/HT46C65 Program Counter+1 OV ...
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... Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 Affected flag(s) TO PDF Rev. 1.80 HT46R65/HT46C65 Stack Stack ...
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... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO PDF Rev. 1.80 HT46R65/HT46C65 ...
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... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO PDF Rev. 1.80 HT46R65/HT46C65 ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO PDF Rev. 1.80 HT46R65/HT46C65 ([m]+1) ...
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... Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO PDF Rev. 1.80 HT46R65/HT46C65 ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO PDF Rev. 1.80 HT46R65/HT46C65 ...
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... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO PDF Rev. 1.80 HT46R65/HT46C65 ...
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... Package Information 52-pin QFP (14´14) Outline Dimensions Symbol Min. A 17.3 B 13.9 C 17 0.73 K 0.1 0 Rev. 1.80 HT46R65/HT46C65 Dimensions in mm Nom. Max. 17.5 14.1 17.5 14.1 1 0.4 3.1 3.4 0.1 1.03 0 July 14, 2005 ...
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... SSOP (300mil) Outline Dimensions Symbol Min. A 395 B 291 C 8 720 Rev. 1.80 HT46R65/HT46C65 Dimensions in mil Nom. Max. 420 299 12 730 July 14, 2005 ...
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... QFP (14´20) Outline Dimensions Symbol Min. A 18.50 B 13.90 C 24.50 D 19. 2. 0.10 0 Rev. 1.80 HT46R65/HT46C65 Dimensions in mm Nom. Max. 19.20 14.10 25.20 20.10 0.65 0.30 3.10 3.40 0.10 1.40 0. July 14, 2005 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.80 HT46R65/HT46C65 48 July 14, 2005 ...