BCM5632E Broadcom Corporation, BCM5632E Datasheet - Page 2

• Manufacturer Part Number: BCM5632E
• Description: 12 GIGABIT + 1 10-GIGABIT SWITCHING PROCESSOR
• Manufacturer: Broadcom Corporation

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or its subsidiaries in the United States and certain other countries. All other trademarks mentioned are the
property of their respective owners.
BROADCOM CORPORATION
16215 Alton Parkway, P.O. Box 57013
Irvine, California 92619-7013
© 2004 by BROADCOM CORPORATION. All rights reserved.
5632E-PB01-R
The BCM5632E switching processor chip supports 12 Gigabit ports and
one 10-Gigabit uplink with all ports in wirespeed operation. The
BCM5632E is ideal for applications such as multi-Gigabit port switches
or aggregating multiple-Gigabit ports to a 10-Gigabit backplane.
For Gigabit ports, the BCM5632E supports PCS (802.3z, 1000BASE-X)
or GMII (802.3ab, 1000BASE-T) interfaces with full-duplex operation
at Gigabit speed, and full- or half-duplex operation at 10/100 Mbps speed
(using 1000BASE-T). For the uplink port, the BCM5632E supports
XGMII.
The BCM5632E supports 802.1Q VLAN tagging as an option (Qon).
The BCM5632E supports 802.1v VLAN Classification by Protocol.
There are four user-programmable protocols that can be set up per port
by the VLAN Classification EtherType and the VLAN Priority/TAG
registers.
The BCM5632E supports 32K internal MAC addresses which are shared
by all ports. Multicast MAC addresses including IP multicast can also be
stored and searched.
The BCM5632E also supports 4K VLAN addresses with the 802.1s
Multiple Spanning Tree option, and flexible and programmable ingress
and egress checking rules for VLAN processing.
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, the pulse logo, and Connecting everything
07/08/04
10 G MAC
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to
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are trademarks of Broadcom Corporation and/
G MAC
G-Port
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The BCM5632E also supports 802.3ad port aggregation. The 12-Gigabit
ports can form up to six trunks, with a maximum of twelve ports in a
trunk. The distribution algorithm is user-selectable. The Link
Aggregation Control Protocol (LACP) frames are handled by the
accompanying CPU and the marker protocol is handled in hardware.
The BCM5632E can be initialized and configured by an EEPROM or a
CPU, which is also responsible for search table updates and management
functions. The CPU is a separate port to the device, containing its own
Tx FIFO and Rx FIFO. The device implements a 32-bit, 33-MHz
Peripheral Component Interconnect (PCI) for flexible CPU selection and
interface.
Other features include frame trapping and forwarding to the CPU, port
monitoring, and broadcast storm control to reduce broadcast traffic
through the switch. The BCM5632E also offers a flexible multiplexer
mode in which the L2 switching functionality can be turned on and off
on a per-port basis.
Manager
Counters
Port
MIB
Maintenance
L2 MAC
Interface
VLAN
Table
Table
Table
PCI
To CPU
Phone: [phone]
Fax: [phone]
E-mail: [e-mail]
Web: www.broadcom.com