BCM1125H Broadcom, BCM1125H Datasheet - Page 2

• Manufacturer Part Number: BCM1125H
• Description: High Performance MIPS Processor
• Manufacturer: Broadcom

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1125H-PB03-R
Broadcom’s BCM1125H product is a state-of-the-art processor solution
targeted at the fast-growing networking, wireless communications,
storage, server/networking appliance and imaging markets. BCM1125H
processors offer industry-leading performance, high functional
integration, and low power levels in a small package required by next-
generation networking applications.
The BCM1125H is software-compatible with the dual-processors
BCM1250, BCM1255, and BCM1280 as well as with the quad-core
processors BCM1455 and BCM1480. All these processors and share
development and modeling tools, firmware, and operating systems with
the processor. The BCM1125H processors are intelligent systems on a
chip consisting of a Broadcom SB-1 high performance MIPS64 CPU, a
shared 256-KB L2 cache, a DDR memory controller, and an integrated
I/O. All major blocks of the processor are connected together via the
ZBbus, a high-speed, low-latency, split-transaction, memory-coherent
bus. The bus implements the standard MESI protocol to ensure
coherency between the CPU, L2 cache, I/O agents, and memory.
Two Gigabit Ethernet MACs (10/100/1000) enable easy interfacing to
LANs. To enable higher data rates, or in cases where Ethernet protocol
processing is not required, each MAC can be configured as an 8-bit
®
, the pulse logo, Connecting everything
05/11/06
55 Mbps
55 Mbps
®
Interrupt/
Interface
Interface
PCMCIA
SMBus
Serial
Serial
GPIO/
Dual
®
, and the Connecting everything logo are among the
Debug/ Bus
DMA
DMA
Trace
Generic I/O
I/O Bridge
Interface
1 Gbps
Flash
BCM1125H Block Diagram
and
O V E R V I E W
SB_1
Core
10/100/
2 x GMII / 16-bit FIFO
@ 2 Gbps / @ 6 Gbps
SB_1
Core
DMA
1000
MAC
FIFO
1/2 core clock
256 Bits
packet FIFO, or both can be combined into a 16-bit packet FIFO. High-
speed I/O is provided using a 66-MHz (rev 2.2) PCI local bus and 8-bit
wide HyperTransport™ (HT) interface.
Two serial ports are provided for WAN connections at up to T3/OC-1
rates (55 Mbps). To enable low-chip-count systems, the BCM1125H
processors also include a configurable generic bus that allows glueless
connection of a boot ROM or FLASH memory and simple I/O
peripherals. On-chip debugging, tracing, and performance monitoring
functions assist both hardware and software designers in debugging and
tuning the system. The system can be run in either big- or little-endian
mode. The BCM1125H processors are manufactured in TSMC's 0.13-µ
process, and are packaged in pin-compatible 31-mm BGA packages.
Implementation of MIPS64 ISA
The SB-1 CPU core is a high-performance implementation of the
standard MIPS64 Instruction Set Architecture (ISA), and incorporates
the MIPS-3D and MIPS-MDMX Application Specific Extensions
(ASEs). The core supports a four-issue enhanced skew pipeline and can
dispatch up to two memory and two ALU (Integer, Floating Point,
MDMX or MIPS-3D) instructions per cycle.
10/100/
DMA
MAC
1000
L2 Cache
256K
2 Gbps
32-Bit
PCI
PCI/HT Bridge
Mover
Data
Controller
HT Host
Memory
Bridge
DDR
Phone: [phone]
Fax: [phone]
E-mail: [e-mail]
Web: www.broadcom.com
8-25 Gbps