LMX2485E National Semiconductor, LMX2485E Datasheet - Page 22

• Manufacturer Part Number: LMX2485E
• Description: High Performance Delta-Sigma Low Power Dual PLLatinum Frequency Synthesizers
• Manufacturer: National Semiconductor

www.national.com
Functional Description
1.8 CYCLE SLIP REDUCTION AND FASTLOCK
The LMX2485 offers both cycle slip reduction (CSR) and
Fastlock with timeout counter support. This means that it
requires no additional programming overhead to use them. It
is generally recommended that the charge pump current in
the steady state be 8X or less in order to use cycle slip
reduction, and 4X or less in steady state in order to use
Fastlock. The next step is to decide between using Fastlock
or CSR. This determination can be made based on the ratio
of the comparison frequency ( f
( BW ).
Cycle Slip Reduction (CSR)
Cycle slip reduction works by reducing the comparison fre-
quency during frequency acquisition while keeping the same
loop bandwidth, thereby reducing the ratio of the comparison
frequency to the loop bandwidth. In cases where the ratio of
the comparison frequency exceeds about 100 times the loop
bandwidth, cycle slipping can occur and significantly de-
grade lock times. The greater this ratio, the greater the
benefit of CSR. This is typically the case of high comparison
frequencies. In circumstances where there is not a problem
with cycle slipping, CSR provides no benefit. There is a glitch
when CSR is disengaged, but since CSR should be disen-
gaged long before the PLL is actually in lock, this glitch is not
an issue. A good rule of thumb for CSR disengagement is to
do this at the peak time of the transient response. Because
this time is typically much sooner than Fastlock should be
disengaged, it does not make sense to use CSR and Fast-
lock in combination.
Fastlock
Fastlock works by increasing the loop bandwidth only during
frequency acquisition. In circumstances where the compari-
son frequency is less than or equal to 2 MHz, Fastlock may
provide a benefit beyond what CSR can offer. Since Fastlock
also reduces the ratio of the comparison frequency to the
loop bandwidth, it may provide a significant benefit in cases
where the comparison frequency is above 2 MHz. However,
CSR can usually provide an equal or larger benefit in these
cases, and can be implemented without using an additional
resistor. The reason for this restriction on frequency is that
Fastlock has a glitch when it is disengaged. As the time of
engagement for Fastlock decreases and becomes on the
order of the fast lock time, this glitch grows and limits the
benefits of Fastlock. This effect becomes worse at higher
comparison frequencies. There is always the option of re-
ducing the comparison frequency at the expense of phase
noise in order to satisfy this constraint on comparison fre-
quency. Despite this glitch, there is still a net improvement in
lock time using Fastlock in these circumstances. When using
Fastlock, it is also recommended that the steady state
charge pump state be 4X or less. Also, Fastlock was origi-
f
(Continued)
COMP
f
f
COMP
COMP
Comparison
1.25 MHz
Frequency
( f
≤ 1.25 MHz
COMP
>
≤ 2 MHz
2 MHz
)
<
Noticeable better
than CSR
Marginally better
than CSR
Same or worse
than CSR
Fastlock
COMP
(Note 9)
) to loop bandwidth
Likely to provide
a benefit,
provided that
f
BW
COMP
Reduction
Cycle Slip
( CSR )
>
100 X
22
nally intended only for second order filters, so when imple-
menting it with higher order filters, the third and fourth poles
can not be too close in, or it will not be possible to keep the
loop filter well optimized when the higher charge pump cur-
rent and Fastlock resistor are engaged.
1.8.1 Using Cycle Slip Reduction (CSR) to Avoid Cycle
Slipping
Once it is decided that CSR is to be used, the cycle slip
reduction factor needs to be chosen. The available factors
are 1/2, 1/4, and 1/16. In order to preserve the same loop
characteristics, it is recommended that the following con-
straint be satisfied: (Fastlock Charge Pump Current) /
(Steady State Charge Pump Current) = CSR
In order to satisfy this constraint, the maximum charge pump
current in steady state is 8X for a CSR of 1/2, 4X for a CSR
of 1/4, and 1X for a CSR of 1/16. Because the PLL phase
noise is better for higher charge pump currents, it makes
sense to choose CSR only as large as necessary to prevent
cycle slipping. Choosing it larger than this will not improve
lock time, and will result in worse phase noise.
Consider an example where the desired loop bandwidth in
steady state is 100 kHz and the comparison frequency is 20
MHz. This yields a ratio of 200. Cycle slipping may be
present, but would not be too severe if it was there. If a CSR
factor of 1/2 is used, this would reduce the ratio to 100 during
frequency acquisition, which is probably sufficient. A charge
pump current of 8X could be used in steady state, and a
factor of 16X could be used during frequency acquisition.
This yields a ratio of 1/2, which is equal to the CSR factor
and this satisfies the above constraint. In this circumstance,
it could also be decided to just use 16X charge pump current
all the time, since it would probably have better phase noise,
and the degradation in lock time would not be too severe.
1.8.2 Using Fastlock to Improve Lock Times
Once it is decided that Fastlock is to be used, the loop
bandwidth multiplier, K, is needed in order to determine the
theoretical impact of Fastlock on the loop bandwidth and the
resistor value, R2p, that is switched in parallel during Fast-
lock. This ratio is calculated as follows: K = ( Fastlock
Charge Pump Current ) / ( Steady State Charge Pump
Current )
The above table shows how to calculate the Fastlock resistor
and theoretical lock time improvement, once the ratio , K, is
16
K
1
2
3
4
8
9
Loop Bandwidth
1.00 X
1.41 X
1.73 X
2.00 X
2.83 X
3.00 X
4.00 X
R2p Value
R2/0.41
R2/0.73
R2/1.83
Open
R2/2
R2/3
20087740
R2
Lock Time
100 %
71 %
58%
50%
35%
33%
25%