LMX2310 National Semiconductor, LMX2310 Datasheet - Page 25

• Manufacturer Part Number: LMX2310
• Description: PLLatinum Ultra Low Power Frequency Synthesizer for RF Personal Communications
• Manufacturer: National Semiconductor

Register
2.0 Power-Down
The LMX2310/1/2/3U are power controlled through logical
control of the CE pin in conjunction with programming of the
PDWN and CPo_TRI bits. A truth table is provided that
describes how the state of the CE pin, the PDWN bit and
CPo_TRI bit set the operating mode of the device. A com-
plete programming description of Power-Down is provided in
Section 3.3.1.
When the device enters the power-down mode, the oscillator
buffer, RF prescaler, phase detector, and charge pump cir-
cuits are all disabled. The OSC
are all forced to a high impedance state. The reference
divider and feedback divider circuits are disabled and held at
3.0 Programming Description
3.1 MICROWIRE INTERFACE
The MICROWIRE interface is comprised of a 22-bit shift register and three control registers. The shift register consists of a 20-bit
DATA field and a 2-bit address (ADDR) field as shown below. Data is loaded into the shift register on the rising edges of the
CLOCK signal MSB first. When Latch Enable transitions HIGH, data stored in the shift register is loaded into either the R, N or
T register depending on the state of the ADDR bit. The DATA field assignments for the R, N and T registers are shown in Section
3.1.1.
3.1.1 Register Map
X = Don’t Care
CE
R
N
T
0
1
1
1
PWDN CPo_TRI
PWDN
FoLD1
X
0
1
1
21
0
Most Significant Bit
FoLD0
X
20
0
0
1
P
0
MSB
21
Power-down (Asynchronous)
Normal Operation
Power-down (Synchronous)
Power-down (Asynchronous)
CPo_
TRI
19
0
IN
, CPo, F
Operating Mode
CP0_
18
4x
0
DATA
IN
POL
PD_
17
, F
0
INB
ADDR
16
, LD pins
0
1
2
0
SHIFT REGISTER BIT LOCATION
B_CNTR[12:0]
15
0
Data Field
FoLD2
2
14
25
Target Register
R register
N register
T register
the load point during power-down. When the device is pro-
grammed to normal operation, the oscillator buffer, RF pres-
caler, phase detector, and charge pump circuits are all pow-
ered on. The feedback divider and the reference divider are
held at the load point. This allows the RF prescaler, feedback
divider, reference oscillator, the reference divider and pres-
caler circuitry to reach proper bias levels. After a 1.5 µs
delay, the feedback and reference divider are enabled and
they resume counting in “close” alignment (The maximum
error is one prescaler cycle). The MICROWIRE control reg-
ister remains active and capable of loading and latching in
data while in the power-down mode.
The synchronous power-down function is gated by the
charge pump. When the device is configured for synchro-
nous power-down, the device will enter the power-down
mode upon the completion of the next charge pump pulse
event.
The asynchronous power-down function is NOT gated by the
completion of a charge pump pulse event. When the device
is configured for asynchronous power-down, the part will go
into power-down mode immediately.
13
12
R_CNTR[14:0]
ADDRESS
11
10
TO_CNTR[11:0]
9
8
7
LSB
6
A_CNTR[4:0]
0
5
Least Significant Bit
4
3
2
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Address
1
0
0
1
Field
0
0
1
0