MC74HC165A Motorola, MC74HC165A Datasheet - Page 5

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MC74HC165A

Manufacturer Part Number
MC74HC165A
Description
8-Bit Serial or Parallel-Input/Serial-Output Shift Register
Manufacturer
Motorola
Datasheet

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High–Speed CMOS Logic Data
DL129 — Rev 6
INPUTS
A, B, C, D, E, F, G, H (Pins 11, 12, 13, 14, 3, 4, 5, 6)
nously entered in parallel into the internal flip–flops when the
Serial Shift/Parallel Load input is low.
SA (Pin 10)
is high, data on this pin is serially entered into the first stage
of the shift register with the rising edge of the Clock.
CONTROL INPUTS
Serial Shift/Parallel Load (Pin 1)
this pin, data at the Serial Data input (SA) are shifted into the
register with the rising edge of the Clock. When a low level is
Parallel Data inputs. Data on these inputs are asynchro-
Serial Data input. When the Serial Shift/Parallel Load input
Data–entry control input. When a high level is applied to
PIN DESCRIPTIONS
5
applied to this pin, data at the Parallel Data inputs are
asynchronously loaded into each of the eight internal stages.
Clock, Clock Inhibit (Pins 2, 15)
Either may be used as an active–high clock inhibit. However,
to avoid double clocking, the inhibit input should go high only
while the clock input is high.
down to DC in a continuous or intermittent mode.
OUTPUTS
Q H , Q H (Pins 9, 7)
noninverted and inverted outputs of the eighth stage of the
shift register.
Clock inputs. These two clock inputs function identically.
The shift register is completely static, allowing Clock rates
Complementary Shift Register outputs. These pins are the
MC54/74HC165A
MOTOROLA

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