MC705P6A Motorola, MC705P6A Datasheet - Page 40

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MC705P6A

Manufacturer Part Number
MC705P6A
Description
Microcontrollers
Manufacturer
Motorola
Datasheet

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Input/Output Ports
At power-on or reset, all DDRs are cleared, which configures all port pins as inputs. The DDRs are
capable of being written to or read by the processor. During the programmed output state, a read of the
data register will actually read the value of the output data latch and not the level on the I/O port pin.
40
To avoid generating a glitch on an I/O port pin, data should be written to the
I/O port data register before writing a logic 1 to the corresponding data
direction register.
DDRA
DDRB
DDRC
DDRD
Note: Does not affect input, but stored to data register
Note: Does not affect input, but stored to data register
Note: Does not affect input, but stored to data register
Notes:
0
1
0
1
0
1
0
1
1. Does not affect input, but stored to data register
2. PD7 is input only
I/O Pin Mode
I/O Pin Mode
I/O Pin Mode
I/O Pin Mode
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
IN, Hi-Z
IN, Hi-Z
IN, Hi-Z
IN, Hi-Z
OUT
OUT
OUT
OUT
Table 6-1. Port A I/O Functions
Table 6-2. Port B I/O Functions
Table 6-3. Port C I/O Functions
Table 6-4. Port D I/O Functions
DDRC0–DDRC7
DDRC0–DDRC7
DDRA0–DDRA7
DDRA0–DDRA7
DDRB5–DDRB7
DDRB5–DDRB7
DDRA @ $0004
DDRB @ $0005
DDRC @ $0006
DDRD @ $0007
Accesses to
Accesses to
Accesses to
Accesses to
Read/Write
Read/Write
Read/Write
Read/Write
NOTE
DDRD5
DDRD5
PC0–PC7
PB5–PB7
PA0–PA7
I/O Pin
I/O Pin
I/O Pin
I/O Pin
Read
Read
Read
Read
PD5
Accesses to Data
Register @ $0000
Accesses to Data
Register @ $0001
Accesses to Data
Register @ $0002
Accesses to Data
Register @ $0003
See Note 1
PB5–PB7
PC0–PC7
See Note
PA0–PA7
See Note
See Note
Write
Write
Write
Write
PD5
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