CY7C4221-15JXC Cypress Semiconductor Corp, CY7C4221-15JXC Datasheet - Page 5

• Manufacturer Part Number: CY7C4221-15JXC
• Description: IC SYNC FIFO MEM 1KX9 32-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4221-15JXC

• Access Time: 10ns
• Memory Size: 9K (1K x 9)
• Package / Case: 32-PLCC
• Function: Synchronous
• Data Rate: 100MHz
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Data Bus Width: 9 bit
• Bus Direction: Unidirectional
• Timing Type: Synchronous
• Organization: 1 K x 9
• Maximum Clock Frequency: 66.7 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 35 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-06016 Rev. *B
Width Expansion Configuration
Word width may be increased simply by connecting the corre-
sponding input controls signals of multiple devices. A
composite flag should be created for each of the end-point
status flags (EF and FF). The partial status flags (PAE and
PAF) can be detected from any one device. Figure 2 demon-
strates a 18-bit word width by using two CY7C42X1s. Any
word width can be attained by adding additional CY7C42X1s.
When the CY7C42X1 is in a Width Expansion Configuration,
the Read Enable (REN2) control input can be grounded (See
Figure 2). In this configuration, the Write Enable 2/Load
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Figure 2. Block Diagram of 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 Synchronous FIFO Memory
Write
PROGRAMMABLE (PAF)
Write
DATA IN (D)
Write
FULL FLAG (FF) # 1
FULL FLAG (FF) # 2
ENABLE 1 (WEN1)
ENABLE 2/LOAD
CLOCK (WCLK)
(WEN2/LD)
18
9
Read Enable 2 (REN2)
FF
RESET (RS)
CY7C42X1
Used in a Width Expansion Configuration
EF
9
9
Flag Operation
The CY7C42X1 devices provide four flag pins to indicate the
condition of the FIFO contents. Empty, Full, PAE, and PAF are
synchronous.
Full Flag
The Full Flag (FF) will go LOW when device is full. Write opera-
tions are inhibited whenever FF is LOW regardless of the state
of WEN1 and WEN2/LD. FF is synchronized to WCLK, i.e., it
is exclusively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN1 and REN2. EF is synchronized
to RCLK, i.e., it is exclusively updated by each rising edge of
RCLK.
Read Enable 2 (REN2)
FF
RESET (RS)
CY7C42X1
CY7C4421/4201/4211/4221
EF
CY7C4231/4241/4251
EMPTY FLAG (EF) #1
EMPTY FLAG (EF) #2
Read CLOCK (RCLK)
Read ENABLE 1 (REN1)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
9
DATA OUT (Q)
42X1–16
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