LM4918LQ National Semiconductor, LM4918LQ Datasheet - Page 15

• Manufacturer Part Number: LM4918LQ
• Description: Stereo Audio Amp with AGC Control
• Manufacturer: National Semiconductor

Application Information
negative peak circuit is described by jumpers in place on S2
and S4, while removed from S1 and S3. Operating in the
negative manner places the Vpk_Bfr directly to VagcRef, and
makes Vpk_in the effective AGC gain reference voltage.
Keep in mind this will reverse the voltage values used for a
given AGC gain level as compared to VagcRef values.
The peak detect period is set by the Chold capacitor as
described in the AUTOMATIC GAIN CONTROL section.
AGC gain will slowly increase to maximum set value at a rate
determined by Chold. Decreasing Chold results in faster
peak hold times and faster gain increase after a peak-
induced gain reduction.
SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires high value
input coupling capacitor (C7 and C8 in Figure 2). A high
value capacitor can be expensive and may compromise
space efficiency in portable designs. In many cases, how-
ever, the speakers used in portable systems, whether inter-
nal or external, have little ability to reproduce signals below
150Hz. Applications using speakers with this limited fre-
quency response reap little improvement by using large
input capacitor.
The LM4918 actually has two different sets of input coupling
caps: one for the AGC block (C7 and C8) and one for the
power amplifier block (C1 and C5). These must both be in
place to properly protect the inputs from DC offsets and
should match for predictable frequency response.
The internal input resistor (R1 and R6) and the input capaci-
tor (C1 and C5) produce a high pass filter cutoff frequency
that is found using Equation (7).
As an example when using a speaker with a low frequency
limit of 150Hz, C
C
ciency, full range speaker whose response extends below
20Hz.
Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consid-
eration should be paid to value of C
nected to the Vbypass pin. Since C
LM4918 settles to quiescent operation, its value is critical
when minimizing turn-on pops. The slower the LM4918’s
outputs ramp to their quiescent DC voltage (nominally V
2), the smaller the turn-on pop. Choosing C
along with a small value of C
0.49µF), produces a click-less and pop-less shutdown func-
tion.
Output Capacitor Value Selection
Amplifying the lowest audio frequencies also requires the
use of a high value output coupling capacitor (C10 and C11
in Figure 2). A high value output capacitor can be expensive
and may compromise space efficiency in portable design.
The speaker load (R) and the output capacitor (C) form a
high pass filter with a low cutoff frequency determined using
Equation (7).
i
shown in Figure 2 allows the LM4918 to drive high effi-
i
, using Equation (7) is 0.063µF. The 0.49µF
f
c
= 1 / (2πRC)
i
(in the range of 0.1µF to
B
determines how fast the
B
, the capacitor con-
(Continued)
B
equal to 2.2µF
DD
(7)
/
15
When using a typical headphone load of R
frequency limit of 50Hz, C
Figure 2 allows the LM4857 to drive a headphone whose
frequency response extends below 50Hz.
Cstdby Value Selection
Cstdby is set to provide a large enough delay time on the
threshold detect such that the device does not inadvertently
toggle in and out of Standby mode when in MODE 1 and low
level music passages are playing. This should be set for
delay periods of several seconds. The demo board uses a
10uF cap that results in about 10s (typ) of delay time before
entering Standby (MODE 1 must be enabled, Standby must
be enabled, and the input level must remain below the
threshold level for 10s). Smaller values may result in
Standby activation during extended low periods of music.
PCB LAYOUT GUIDELINES
This section provides practical guidelines for mixed signal
PCB layout that involves various digital/analog power and
ground traces. Designers should note that these are only
"rule-of-thumb" recommendations and the actual results will
depend heavily on the final layout.
GENERAL MIXED SIGNAL LAYOUT
RECOMMENDATION
Power and Ground Circuits
For 2 layer mixed signal design, it is important to isolate the
digital power and ground trace paths from the analog power
and ground trace paths. Star trace routing techniques (bring-
ing individual traces back to a central point rather than daisy
chaining traces together in a serial manner) can have a
major impact on low level signal performance. Star trace
routing refers to using individual traces to feed power and
ground to each circuit or even device. This technique will
require a greater amount of design time but will not increase
the final price of the board. The only extra parts required will
be some jumpers.
Single-Point Power / Ground Connections
The analog power traces should be connected to the digital
traces through a single point (link). A "Pi-filter" can be helpful
in minimizing High Frequency noise coupling between the
analog and digital sections. It is further recommended to put
digital and analog power traces over the corresponding digi-
tal and analog ground traces to minimize noise coupling.
Placement of Digital and Analog Components
All digital components and high-speed digital signal traces
should be located as far away as possible from analog
components and circuit traces.
Avoiding Typical Design / Layout Problems
Avoid ground loops or running digital and analog traces
parallel to each other (side-by-side) on the same PCB layer.
When traces must cross over each other do it at 90 degrees.
Running digital and analog traces at 90 degrees to each
other from the top to the bottom side as much as possible will
minimize capacitive noise coupling and cross talk.
O
is 99µF. The 200µF C
L
= 32Ω with a low
www.national.com
O
shown in