SA25F010 Saifun, SA25F010 Datasheet - Page 28
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SA25F010
Manufacturer Part Number
SA25F010
Description
1Mb Serial Flash
Manufacturer
Saifun
Datasheet
1.SA25F010.pdf
(37 pages)
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Part Number:
SA25F010LMNFX
Manufacturer:
SAIFUN
Quantity:
20 000
Sector Erase (SE)
The SE instruction sets all 256 Kb in the
selected sector to 1. Before it can be
executed, two separate instructions must
be carried out. The device must first be
write enabled via the WREN instruction,
and then a SE sequence, which consists of
four bytes, may be executed. The address
of the memory locations to be written must
be inside the sector to be erased and
outside the protected address field location
selected by the Block Write Protection
level. During an internal SE cycle, all
commands are ignored except the RDSR
instruction.
A SE instruction requires the following
sequence:
1.
2.
SCK
CS
After the CSb line is pulled low to
select the device, the SE opcode is
transmitted via the SI line, followed
by the 3-byte address.
Erasing begins after the CSb pin is
brought
low-to-high transition must occur
during
immediately after the clock in the
last address bit.
SI
the
high.
SCK
0
The
Figure 20. Sector Erase (SE) Instruction Sequence
1
low
CSb
2
Instruction
3
time,
pin's
4
5
6
7
MSB
23
8
As soon as CSb is driven high, the
self-timed SE cycle (whose duration is
defined as T
cycle is in progress, the status register
may be read to check the value of the
/RDY bit. The /RDY bit is 1 during the
self-timed SE cycle, and 0 when it is
completed. The WEN bit is reset at some
unspecified time before the cycle is
completed. The instruction sequence is
shown in Figure 20.
The SA25F010 is automatically returned to
the write disable state at the completion of
an SE cycle.
22
9
NOTES:
1. If the device is not write enabled,
2. A SE instruction applied to a sector
24 Bit Address
21
10
the
instruction
standby state when CSb is brought
high. A new CSb falling edge is
required to re-initiate the serial
communication.
that is protected by the Block
Protect
described in Table 8, page 18, and
Table 9, page 21) is not executed.
28
3
device
SE
29
) is initiated. While the SE
2
(BP1,
SA25F010 Advanced Information
30
and
1
ignores
31
0
BP0)
returns
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bits
the
to
SAIFUN
the
(as
SE
28