74AUP2G79 NXP Semiconductors, 74AUP2G79 Datasheet
74AUP2G79
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74AUP2G79 Summary of contents
Page 1
... The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation ...
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... Package Temperature range Name 74AUP2G79DC +125 C 74AUP2G79GT +125 C 74AUP2G79GM +125 C 4. Marking Table 2. Marking codes Type number 74AUP2G79DC 74AUP2G79GT 74AUP2G79GM 5. Functional diagram 1D 1CP 2D 2CP 001aah811 Fig 1. Logic symbol CP D Fig 3. Logic diagram (one flip-flop) 74AUP2G79_2 Product data sheet Low-power dual D-type fl ...
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... Rev. 02 — 19 March 2008 74AUP2G79 2CP 74AUP2G79 terminal 1 index area 2CP 3 5 001aaf270 Transparent top view Pin configuration SOT902-1 (XQFN8U) © NXP B.V. 2008. All rights reserved. ...
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... Active mode and Power-down mode +125 C amb derates linearly with 8.0 mW/K. tot derates linearly with 2.4 mW/K. tot Conditions Active mode Power-down mode 0 3 Rev. 02 — 19 March 2008 74AUP2G79 Output Min Max Unit 0.5 +4 [1] 0.5 +4 ...
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... GND 0 3 per pin GND GND Rev. 02 — 19 March 2008 74AUP2G79 Min Typ Max ...
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... GND 0 3 per pin 0 3 Rev. 02 — 19 March 2008 74AUP2G79 Min Typ Max ...
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... GND 0 3 per pin 0 3 GND. CC Rev. 02 — 19 March 2008 74AUP2G79 Min Typ Max ...
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... Figure 23 1.3 V 3.1 6 1.6 V 2.5 4 1.95 V 2.1 3 2.7 V 1.8 2 3.6 V 1.7 2.5 Figure 192 = 1 1 324 = 1. 1. 421 = 2 2 486 = 3 3 550 Rev. 02 — 19 March 2008 74AUP2G79 + +125 C Unit Max Min Max Min - - - - 11.0 2.4 12.9 2.4 7.0 1.8 8.1 1.8 5.4 1.5 6.4 1.5 4.0 1.1 4.7 1.1 3.4 0.9 4.0 0 170 - 170 - 310 - ...
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... Figure 36 1.3 V 4.7 9 1.6 V 3.8 6 1.95 V 3.3 5 2.7 V 3.0 4 3.6 V 2.8 3.9 Figure 128 = 1 1 206 = 1. 1. 262 = 2 2 269 = 3 3 309 Rev. 02 — 19 March 2008 74AUP2G79 + +125 C Unit Max Min Max Min - - - - 13.6 3.2 15.6 3.2 9.2 2.5 10.7 2.5 7.1 2.2 8.5 2.2 5.4 1.9 6.3 1.9 4.5 1.6 5.0 1 120 - 120 - 190 - ...
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... 0 0 0 0.7 Figure 1 0 0 0 0 0 5 2 1 0 0 0.6 Rev. 02 — 19 March 2008 74AUP2G79 + +125 C Unit Max Min Max Min - - - - - 1.5 - 1.5 - 1.0 - 1.0 - 0.9 - 0.9 - 0.7 - 0.7 - 0 1.6 - 1.6 - 1.0 - 1.0 - 0.9 - 0.9 - 0.9 - ...
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... V M GND t PHL output Table 9. are typical output voltage levels that occur with the output load. OH Rev. 02 — 19 March 2008 74AUP2G79 + +125 C Unit Max Min Max Min - - - - - - - - - - - ...
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... PHL Table 9. are typical output voltage drop that occur with the output load. OH Input 0 Rev. 02 — 19 March 2008 74AUP2G79 1/f max t PLH 001aaf272 3 © NXP B.V. 2008. All rights reserved ...
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... For measuring propagation delays, set-up times, hold times and pulse width, R 74AUP2G79_2 Product data sheet Low-power dual D-type flip-flop; positive-edge trigger DUT R T 10. [ Rev. 02 — 19 March 2008 74AUP2G79 V EXT 001aac521 of the pulse generator EXT PLH PHL ...
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... Low-power dual D-type flip-flop; positive-edge trigger pin 1 index 2.5 scale (1) ( 0.27 0.23 2.1 2.4 0.12 0.5 0.17 0.08 1.9 2.2 REFERENCES JEDEC JEITA MO-187 Rev. 02 — 19 March 2008 74AUP2G79 detail 3.2 0.40 0.21 0.4 0.2 0.13 0.1 3.0 0.15 0.19 EUROPEAN PROJECTION SOT765-1 A (1) ...
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... Low-power dual D-type flip-flop; positive-edge trigger scale 1.05 0.35 0.40 0.6 0.5 0.95 0.27 0.32 REFERENCES JEDEC JEITA - - - MO-252 Rev. 02 — 19 March 2008 74AUP2G79 4 ( EUROPEAN ISSUE DATE PROJECTION © NXP B.V. 2008. All rights reserved. SOT833-1 07-11-14 07-12- ...
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... scale 1.65 0.35 0.15 0.55 0.5 0.1 1.55 0.25 0.05 REFERENCES JEDEC JEITA MO-255 - - - Rev. 02 — 19 March 2008 74AUP2G79 detail 0.05 0.05 0.05 EUROPEAN PROJECTION © NXP B.V. 2008. All rights reserved. SOT902-1 ISSUE DATE 05-11-25 07-11- ...
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... Data sheet status Product data sheet Figure 1 and Figure 2: pin numbers removed from logic symbols Figure 12: package outline drawing updated to latest version Product data sheet Rev. 02 — 19 March 2008 74AUP2G79 Change notice Supersedes - 74AUP2G79_1 - - © NXP B.V. 2008. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 19 March 2008 74AUP2G79 © NXP B.V. 2008. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 19 March 2008 Document identifier: 74AUP2G79_2 ...