74AUP1T57 Philips Semiconductors, 74AUP1T57 Datasheet

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74AUP1T57

Manufacturer Part Number
74AUP1T57
Description
Low-power Configurable Gate
Manufacturer
Philips Semiconductors
Datasheet

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1. General description
2. Features
The 74AUP1T57 provides low-power, low-voltage configurable logic gate functions. The
output state is determined by eight patterns of 3-bit input. The user can choose the logic
functions AND, OR, NAND, NOR, XNOR, inverter and buffer. All inputs can be connected
to V
This device ensures a very low static and dynamic power consumption across the entire
V
The 74AUP1T57 is designed for logic-level translation applications with input switching
levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single
2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from
3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using I
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the
entire V
CC
74AUP1T57
Low-power configurable gate with voltage-level translator
Rev. 01 — 3 January 2008
Wide supply voltage range from 2.3 V to 3.6 V
High noise immunity
ESD protection:
Low static power consumption; I
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
I
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
CC
OFF
range from 2.3 V to 3.6 V.
HBM JESD22-A114E Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
or GND.
CC
circuitry provides partial Power-down mode operation
range.
CC
= 1.5 A (maximum)
CC
Product data sheet
OFF
. The I
OFF

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74AUP1T57 Summary of contents

Page 1

... This device ensures a very low static and dynamic power consumption across the entire V range from 2 3 The 74AUP1T57 is designed for logic-level translation applications with input switching levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single 2 3.3 V supply voltage. The wide supply voltage range ensures normal operation as battery voltage drops from 3 2.3 V. This device is fully specifi ...

Page 2

... C to +125 C 74AUP1T57GF +125 C 4. Marking Table 2. Marking Type number 74AUP1T57GW 74AUP1T57GM 74AUP1T57GF 5. Functional diagram Fig 1. Logic symbol 74AUP1T57_1 Product data sheet Low-power configurable gate with voltage-level translator Description SC-88 plastic surface-mounted package; 6 leads XSON6 plastic extremely thin small outline package; no leads; ...

Page 3

... Rev. 01 — 3 January 2008 74AUP1T57 74AUP1T57 GND Transparent top view Fig 4. Pin configuration SOT891 (XSON6) Output © NXP B.V. 2008. All rights reserved. ...

Page 4

... 001aab586 Fig 8. 2-input NOR gate or 2-input AND gate with both 001aab588 Fig 10. Inverter Rev. 01 — 3 January 2008 74AUP1T57 and 7 and 001aab585 2-input OR gate with inverted C input A ...

Page 5

... V < Active mode and Power-down mode +125 C amb derates linearly with 4.0 mW/K. tot derates linearly with 2.4 mW/K. tot Conditions Active mode Power-down mode Rev. 01 — 3 January 2008 74AUP1T57 V CC Min Max 0.5 +4 [1] 0.5 +4 [1] 0.5 +4 ...

Page 6

... 3 GND GND Rev. 01 — 3 January 2008 74AUP1T57 Min Typ Max 0.60 - 1.10 0.75 - 1.16 0.35 - 0.60 0.50 - 0.85 0.23 - 0.60 0.25 - 0. ...

Page 7

... 2 3 2 3 2 4 GND Rev. 01 — 3 January 2008 74AUP1T57 Min Typ Max ...

Page 8

... L [2] Figure 3.0 L [2] Figure 3.6 L Rev. 01 — 3 January 2008 74AUP1T57 Min Typ Max - - 0. 0. 3 +125 C [1] Typ Max Min Max (85 C) (125 C) 3.6 5.5 0.5 6.8 4.1 6.2 1.0 7 ...

Page 9

... Figure 2 MHz GND where Rev. 01 — 3 January 2008 74AUP1T57 13 +125 C [1] Typ Max Min Max (85 C) (125 C) 2.8 4.2 0.5 5.3 3.4 4.9 1.0 6.1 3.9 5.5 1.0 6.8 5.0 6.9 1.5 8.5 2.8 4.2 0.5 4.7 3.3 4.9 1.0 5.7 3.8 5.5 1.0 6.2 4.9 7.0 1.5 7.8 3 ...

Page 10

... V M GND t PHL output PLH output Table 10. Input 0 Rev. 01 — 3 January 2008 74AUP1T57 PLH PHL V M 001aab593 1. 3.6 V 3.0 ns © NXP B.V. 2008. All rights reserved ...

Page 11

... Low-power configurable gate with voltage-level translator DUT R T 11. [ for measuring propagation delays, setup and hold times and pulse width R L Rev. 01 — 3 January 2008 74AUP1T57 V EXT 001aac521 of the pulse generator EXT ...

Page 12

... scale 0.25 2.2 1.35 2.2 1.3 0.65 0.10 1.8 1.15 2.0 REFERENCES JEDEC JEITA SC-88 Rev. 01 — 3 January 2008 74AUP1T57 detail 0.45 0.25 0.2 0.2 0.1 0.15 0.15 EUROPEAN PROJECTION © NXP B.V. 2008. All rights reserved. SOT363 ISSUE DATE ...

Page 13

... Low-power configurable gate with voltage-level translator scale 1.05 0.35 0.40 0.6 0.5 0.95 0.27 0.32 REFERENCES JEDEC JEITA MO-252 Rev. 01 — 3 January 2008 74AUP1T57 SOT886 4 ( EUROPEAN ISSUE DATE PROJECTION 04-07-15 04-07-22 © NXP B.V. 2008. All rights reserved ...

Page 14

... Low-power configurable gate with voltage-level translator scale 1.05 0.35 0.40 0.55 0.35 0.95 0.27 0.32 REFERENCES JEDEC JEITA Rev. 01 — 3 January 2008 74AUP1T57 SOT891 4 ( EUROPEAN ISSUE DATE PROJECTION 05-04-06 07-05-15 © NXP B.V. 2008. All rights reserved ...

Page 15

... Revision history Table 13. Revision history Document ID Release date 74AUP1T57_1 20080103 74AUP1T57_1 Product data sheet Low-power configurable gate with voltage-level translator Data sheet status Change notice Product data sheet - Rev. 01 — 3 January 2008 74AUP1T57 Supersedes - © NXP B.V. 2008. All rights reserved ...

Page 16

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 3 January 2008 74AUP1T57 © NXP B.V. 2008. All rights reserved ...

Page 17

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AUP1T57 All rights reserved. Date of release: 3 January 2008 Document identifier: 74AUP1T57_1 ...

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