74ALVCH16501 Philips Semiconductors, 74ALVCH16501 Datasheet - Page 2

• Manufacturer Part Number: 74ALVCH16501
• Description: 18-bit universal bus transceiver 3-State
• Manufacturer: Philips Semiconductors

1. C
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0V; T
NOTES:
ORDERING INFORMATION
56-Pin Plastic TSSOP Type II
1998 Sep 29
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive
Universal bus transceiver with D-type latches and D-type flip-flops
capable of operating in transparent, latched or clocked mode.
All inputs have bushold circuitry
Output drive capability 50 transmission lines @ 85 C
3-State non-inverting outputs for bus oriented applications
18-bit universal bus transceiver (3-State)
t
C
C
C
C
PHL
P
f
o
I/O
I
PD
PD
PD
D
= output frequency in MHz; V
= C
/t
SYMBOL
PLH
is used to determine the dynamic power dissipation (P
PD
amb
V
PACKAGES
= 25 C; t
CC
24 mA at 3.0 V
2
f
i
+ S (C
r
Propagation delay
An, Bn to Bn, An
Input/output capacitance
Input capacitance
Power dissipation capacitance per
latch
= t
f
= 2.5ns
L
V
CC
CC
PARAMETER
= supply voltage in V; S (C
2
f
o
) where: f
TEMPERATURE RANGE
i
= input frequency in MHz; C
–40 C to +85 C
D
in W):
L
V
V
V
V
V
CC
CC
I
I
= GND to V
= GND to V
CC
2
= 2.5V, C
= 3.3V, C
2
DESCRIPTION
The 74ALVCH16501 is an 18-bit universal transceiver featuring
non-inverting 3-State bus compatible outputs in both send and
receive directions. Data flow in each direction is controlled by output
enable (OE
(CP
in the transparent mode when LE
A data is latched if CP
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CP
active. When OE
state.
Data flow for B-to-A is similar to that of A-to-B but uses OE
and CP
High, and OE
To ensure the high impedance state during power up or power
down, OE
OE
minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
f
o
) = sum of outputs.
AB
AB
L
L
CC
CC
should be tied to GND through a pulldown resistor; the
and CP
L
= 30pF
= 50pF
BA
CONDITIONS
1
1
= output load capacitance in pF;
OUTSIDE NORTH AMERICA
. The output enables are complimentary (OE
BA
AB
should be tied to V
74ALVCH16501 DGG
BA
BA
and OE
is active Low).
) inputs. For A-to-B data flow, the device operates
AB
is Low, the outputs are in the high-impedance
AB
BA
Outputs disabled
Outputs enabled
), latch enable (LE
is held at a High or Low logic level. If LE
AB
. When OE
CC
AB
through a pullup resistor and
is High. When LE
74ALVCH16501
AB
AB
TYPICAL
is High, the outputs are
Product specification
and LE
2.8
3.0
8.0
4.0
21
3
DWG NUMBER
853–2091 20106
SOT364-1
BA
AB
AB
), and clock
is Low, the
is active
BA
UNIT
pF
pF
pF
ns
, LE
F
BA
AB