74ALVC374 Philips Semiconductors, 74ALVC374 Datasheet - Page 2

• Manufacturer Part Number: 74ALVC374
• Description: Octal D-type flip-flop positive edge-trigger
• Manufacturer: Philips Semiconductors

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. The condition is V
2002 Feb 26
t
C
C
PHL
SYMBOL
Wide supply voltage range from 1.65 to 3.6 V
Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
3.6 V tolerant inputs/outputs
CMOS LOW power consumption
Direct interface with TTL levels (2.7 to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
ESD protection:
2000 V Human Body Model (JESD22-A 114-A)
200 V Machine Model (JESD22-A 115-A).
I
PD
Octal D-type flip-flop; positive edge-trigger;
3-state
P
f
f
C
V
i
o
/t
D
CC
PD
= input frequency in MHz;
L
PLH
= output frequency in MHz;
= output load capacitance in pF;
= C
is used to determine the dynamic power dissipation (P
= supply voltage in Volts.
PD
amb
propagation delay CP to Q
input capacitance
power dissipation capacitance per buffer
V
CC
= 25 C.
2
I
f
= GND to V
i
+ (C
PARAMETER
L
V
CC
CC
2
.
f
o
n
) where:
V
V
V
V
V
2
CC
CC
CC
CC
CC
outputs enable
outputs disabled
DESCRIPTION
The 74ALVC374 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
The 74ALVC374 is an octal D-type flip-flop featuring
separate D-type inputs for each flip-flop and 3-state
outputs for bus oriented applications. A clock (CP) input
and an output enable (OE) input are common to all
flip-flops.
The eight flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the eight flip-flops is
available at the outputs. When OE is HIGH, the outputs go
to the high-impedance OFF-state. Operation of the
OE input does not affect the state of the flip-flops.
The ‘374’ is functionally identical to the ‘574’, but the ‘574’
has a different pin arrangement.
D
= 1.8 V; C
= 2.5 V; C
= 2.7 V; C
= 3.3 V; C
= 3.3 V; notes 1 and 2
in W).
CONDITIONS
L
L
L
L
= 30 pF; R
= 30 pF; R
= 50 pF; R
= 50 pF; R
L
L
L
L
= 1 k
= 500
= 500
= 500
Product specification
3.1
2.3
2.5
2.5
3.5
21
13
TYPICAL
74ALVC374
ns
ns
ns
ns
pF
pF
pF
UNIT