MC33899 Freescale Semiconductor, MC33899 Datasheet - Page 22

• Manufacturer Part Number: MC33899
• Description: Programmable H-Bridge Power IC
• Manufacturer: Freescale Semiconductor

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SPI Control Register Definition
Fault register, select a programmable current limit, and select
SPI Fault Register Definition
Fault register.
The output load status of the H-Bridge circuit is reported via
the output DO SPI bits. In addition to output fault information,
die temperature warnings and overtemperature conditions
are reported.
22
33899
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
An 8-bit SPI allows the system microprocessor to clear the
The fault diagnostic capability consists of one internal 8-bit
Bit 8: Short to
Bit 7: Short to Ground: 0 = No fault; 1 = S1 or S0 shorted to GND (High-Side Linear Current Limit has tripped)
Bit 6: Open Fault: 0 = No fault; 1 = S1 or S0 is Open Circuited
Bit 5: Overvoltage or Undervoltage: 0 = No fault; 1 = Overvoltage/undervoltage fault
Bit 4: Low-Side Comparator: 0 = No trip; 1 = Tripped
Bit 3: XOR function of EN1, EN2 inputs. 0 = (EN1 same logic level as EN2). 1 = (EN1 not same logic level as EN2).
Bits 2 – 1: Die Temperature
ShVIGNP
8 (MSB)
00 = T < 140°C
01 = 140°C < T < Overtemperature Shutdown
10 = Not Defined
11 = Overtemperature Shutdown (Latched Off)
Bit 8: FLTCLR: 0 = Retain faults; 1 = Clear faults
Bit 7: Not used
Bit 6: Not used
Bit 5: Not used
Bits 4 – 3: Set Low Side Current Comparator Limits
Bits 2 – 1: Slew Time
8 (MSB)
FLTCLR
00 = 4.0 A
01 = 5.0 A
10 = 6.0 A
11 = 8.5 A
00 = 1X
01 = 2X
10 = 4X
11 = 4X
Table 9
VIGNP:
shows the content of the Fault register.
ShGnd
Not Used
0 = No fault; 1 = S1 or S0 shorted to VIGNP (Low-Side Linear Current Limit has tripped)
7
7
SPI INTERFACE AND REGISTER DESCRIPTION
Open Fault
Table 8. SPI Control Register Bit Definitions
Not Used
6
LOGIC COMMANDS AND REGISTERS
Table 9. SPI Fault Register Bit Definitions
6
Overvoltage or
Undervoltage
Not Used
5
5
LS Comparator
Current Limit
a 1X, 2X, or 4X slew rate. The SPI Control Register bit
definitions are shown in
transition, followed by 8 SCLK cycles to shift the fault register
bits out the DO pin. The rising edge of
impedance mode and clears the fault latches if the FLTCLR
bit is set. The thermal fault is immediately set again if the fault
condition is still present. Accurate fault reporting can only be
obtained by reading the DO line at intervals greater than the
fault timer. A thermal fault will be latched as soon as it occurs.
Note At POR, all bits in the register are cleared to 0s.
An SPI read cycle is limited by a
Note At POR, all bits in the register are cleared to 0s.
4
4
Current Limit
EN1, EN2
Status
3
3
Analog Integrated Circuit Device Data
Table
Slew Time
8.
Die Temp
2
Freescale Semiconductor
CS
2
CS
logic [1] to logic [0]
sets DO in a high
Slew Time
1 (LSB)
Die Temp
1 (LSB)