NCP1579 ON Semiconductor, NCP1579 Datasheet - Page 7

• Manufacturer Part Number: NCP1579
• Description: Low Voltage Synchronous Buck Controller
• Manufacturer: ON Semiconductor

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UVLO
unexpected behavior does not occur when V
support the internal rails and power the converter. For the
NCP1579, the UVLO is set to permit operation when
converting from a 5.0 input voltage.
Overcurrent Threshold Setting
ranging from 50 mV to 550 mV, simply by adding a resistor
(RSET) between BG and GND. During a short period of
time following V
10 mA current
determining a voltage drop across R
drop will be sampled and internally held by the device as
Overcurrent Threshold. The OC setting procedure overall
time length is about 6 ms. Connecting a R
between BG and GND, the programmed threshold will be:
is not connected, the device switches the OCP threshold to
a fixed 375 mV value: an internal safety clamp on BG is
triggered as soon as BG voltage reaches 700 mV, enabling
the 375 mV fixed threshold and ending OC setting phase.
The current trip threshold tolerance is ±25 mV. The accuracy
of the set point is best at the highest set point (550 mV). The
accuracy will decrease as the set point decreases.
Current Limit Protection
FET will conduct large currents. The controller will shut
down the regulator in this situation for protection against
overcurrent. The low−side R
the end of each of the LS−FET turn−on duration to sense the
over current trip point. While the LS driver is on, the Phase
voltage is compared to the internally generated OCP trip
voltage. If the phase voltage is lower than OCP trip voltage,
an overcurrent condition occurs and a counter is initiated.
When the counter completes, the PWM logic and both
HS−FET and LS−FET are turned off. The controller has to
Undervoltage Lockout (UVLO) is provided to ensure that
NCP1579 can easily program an Overcurrent Threshold
RSET values range from 5 kW to 55 kW. In case R
In case of a short circuit or overload, the low−side (LS)
I OCth +
CC
(I
rising over UVLO threshold, an internal
OCSET
I OCSET @ R OCSET
) is sourced from BG pin,
R DS(on)
DS(on)
sense is implemented at
OCSET
CC
OCSET
. This voltage
is too low to
resistor
(eq. 1)
http://onsemi.com
OCSET
7
go through a Power On Reset (POR) cycle to reset the OCP
fault.
Drivers
N−channel MOSFETs. This allows the devices to address
high−power as well as low−power conversion requirements.
The gate drivers also include adaptive non−overlap
circuitry. The non−overlap circuitry increase efficiency,
which minimizes power dissipation, by minimizing the
body diode conduction time.
drive circuitry used in the chip is shown in Figure 9.
required, to realize the full benefit of the onboard drivers.
The capacitors between V
and SWN must be placed as close as possible to the IC. The
current paths for the TG and BG connections must be
optimized. A ground plane should be placed on the closest
layer for return currents to GND in order to reduce loop area
and inductance in the gate drive circuit.
The NCP1579 includes gate drivers to switch external
A detailed block diagram of the non−overlap and gate
Careful selection and layout of external components is
FAULT
FAULT
Figure 9. Block Diagram
+
-
+
-
2 V
CC
and GND and between BST
V
CC
1
2
8
4
3
BST
TG
PHASE
BG
GND
R
set