MCP6546T-I/P Microchip Technology, MCP6546T-I/P Datasheet - Page 13

• Manufacturer Part Number: MCP6546T-I/P
• Description: Push-Pull Output Sub-Microamp Comparator
• Manufacturer: Microchip Technology

The trip points for Figures 3-3 and 3-4 are given by:
The output current required to drive V
As explained in Section 3.2, it is important to keep the
non-inverting input below V
3.4
The MCP6548 is a single comparator with a chip select
(CS) option. When CS is pulled high, the supply current
drops to 20 pA (typ), and goes through the CS pin to
V
into a high impedance state. By pulling CS low, the
comparator is enabled. If the CS pin is left floating, the
comparator will not operate properly. Figure 1-1 shows
the output voltage and supply current response to a CS
pulse.
The internal CS circuitry is designed to minimize
glitches when cycling the CS pin. This helps conserve
power, which is especially important in battery powered
applications.
3.5
The open drain output is designed to make level shift-
ing and wired-OR logic easy to implement. The output
can go as high as 10V for 9V battery-powered applica-
tions. The output stage minimizes switching current
(shoot through current from supply to supply) when the
output changes state. See Figures 2-15, 2-17, 2-32
through 2-36 for more information.
3.6
Reasonable capacitive loads (e.g., logic gates) have lit-
tle impact on propagation delay; see Figure 2-27. The
supply current increases with increasing toggle fre-
quency (Figure 2-30), especially with higher capacitive
loads.
V
SS
THL
2002 Microchip Technology Inc.
. When this happens, the comparator output is put
=
V
TLH
V
The MCP6548 Chip Select (CS) Option
Open Drain Output
Capacitive Loads
PU
I
=
O
V
------------------------------------- -
R
H
V
23
=
V
O L
REF
=
+
V
--------------------------
PU
R
R
V
---------------------
R
R
23
F
R
PU
23
23
=
–
PU
+
R
+
23
V
V
R
=
------------------------------------- -
R
OL
R
D D
PU
23
R
DD
F
R
2
+
+
+0.3V when V
23
------------------
R
+
+
R
V
---------------------------- -
2
R
+
V
V
F
REF
R
R
3
+
REF
REF
23
3
R
+
R
F
R
+
3
–
PU
OL
R
V
------------------------------------- -
R
---------------------
R
F
OL
23
23
is:
R
R
+
+
F
F
PU
R
R
+
F
F
R
> V
+
PU
R
DD
PU
.
3.7
In order to maximize battery life in portable applica-
tions, use large resistors and small capacitive loads.
Also, avoid toggling the output more than necessary,
and do not use chip select (CS) to conserve power for
short periods of time; capacitive loads will draw addi-
tional power at start-up.
3.8
Good PC board layout techniques will help you achieve
the performance shown in the specs and Typical Per-
formance Curves. It will also help you minimize EMC
(Electro-Magnetic Compatibility) issues.
3.8.1
In applications where low input bias current is critical,
PC board surface leakage effects and signal coupling
from trace to trace need to be considered.
Surface leakage is caused by a difference in voltage
between traces, combined with high humidity, dust or
other contamination on the board. Under low humidity
conditions, a typical resistance between nearby traces
is 10
to flow; this is greater than the input current of the
The simplest technique to reduce surface leakage is
using a guard ring around sensitive pins (or traces).
The guard ring is biased at the same voltage as the
sensitive pin or trace; Figure 3-5 shows an example of
a typical layout.
FIGURE 3-5:
Circuit schematics for different guard ring implementa-
tions are shown in Figure 3-6. Figure 3-6A biases the
guard ring to the input common mode voltage.
Figure 3-6B biases the guard ring to a reference volt-
age (V
on the node that is the most constant.
family at 25°C (1 pA, typ).
.
12
REF
. A 5V difference would cause 5 pA of current
Battery Life
Layout Considerations
SURFACE LEAKAGE
, which can be ground). Place the guard ring
Example of guard ring layout.
MCP6546/7/8/9
IN-
Guard Ring
IN+
DS21714A-page 13
V
SS