TDA9874A Philips Semiconductors, TDA9874A Datasheet - Page 31

• Manufacturer Part Number: TDA9874A
• Description: Digital TV sound demodulator/decoder
• Manufacturer: Philips Semiconductors

Philips Semiconductors
10.3.3
The default setting after power-on reset is ‘1100 0000’.
Table 17 General configuration register (subaddress 1)
Table 18 Description of the GCONR bits
1999 Dec 03
Digital TV sound demodulator/decoder
P2OUT
BIT
7
7
6
5
4
3
2
1
0
G
ENERAL
AGCSLOW
SYMBOL
AGCOFF
CLRPFR
SIFSEL
P1OUT
P2OUT
P1OUT
STDBY
C
INIT
ONFIGURATION
6
General purpose I/O pins 1 and 2: these bits control the general purpose input/output
pins. The contents of these bits is written directly to the corresponding pins. If an input is
desired, the bits must be set HIGH to allow the pins to be pulled LOW externally. Input
from the pins is reflected in the device status register (see Section 10.4.1). P1OUT is
recommended to be used for switching an SIF trap for the adjacent picture carrier in
designs that employ such a trap.
Standby mode on/off: when STDBY = 1 the TDA9874A is set to the standby mode.
Most functions are disabled and power dissipation is somewhat reduced. When
STDBY = 0, the TDA9874A is in its normal mode of operation. On return from standby
mode, the device is in its Power-on reset mode and needs to be reinitialized with data
defined by the user.
Initialize to default settings: when INIT = 1 it causes initialization of TDA9874A to its
default settings. This has the same effect as a Power-on reset. In the event of a conflict
between the default settings and any bit set HIGH in this register, the bits actually
written to this register will overwrite the default settings. This bit is automatically reset to
LOW after initialization has been completed. When set LOW, the TDA9874A is in its
normal mode of operation.
Clear power failure register: when CLRPFR = 1 it resets the clear power failure
register. This bit is automatically reset to CLRPFR = 0 after bit PFR in the device status
register has been read.
AGC decay time: when AGCSLOW = 1 a longer decay time and larger hysteresis are
selected for input signals with strong video modulation (conventional intercarrier). This
bit has only an effect, when bit AGCOFF = 0. When AGCSLOW = 0, it selects normal
attack and decay times for the AGC and a small hysteresis.
AGC on/off: when AGCOFF = 1 it forces the AGC block to a fixed gain as defined in the
AGC gain register (see Section 10.3.2). When AGCOFF = 0, the AGC function is
enabled and the contents of the AGC gain register are ignored.
SIF input select: when SIFSEL = 1 it selects pin SIF2 for input (recommended for
satellite tuner). When SIFSEL = 0, pin SIF1 (recommended for terrestrial TV) is
selected.
STDBY
R
EGISTER
5
(GCONR)
INIT
4
31
CLRPFR
3
DESCRIPTION
AGCSLOW
2
AGCOFF
Preliminary specification
1
TDA9874A
SIFSEL
0