74F191SJ Fairchild Semiconductor, 74F191SJ Datasheet
74F191SJ
Specifications of 74F191SJ
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74F191SJ Summary of contents
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... Cascadable Ordering Information Order Package Number Number 74F191SC M16A 74F191SJ M16D 74F191PC N16E Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Logic Symbols IEEE/IEC ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 General Description ...
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... Clock (RC) output. The RC output is normally HIGH. When CE is LOW and TC is HIGH, the RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 Description HIGH / LOW the design of multistage counters, as indicated in Figure 1 and Figure 2 ...
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... X No Change (Hold HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition = LOW Pulse Figure 2. Synchronous n-Stage Counter Using Ripple Carry/Borrow Figure 3. Synchronous n-Stage Counter with Gated Carry/Borrow ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 RC Truth Table Mode Note generated internally. ...
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... Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 Figure 4. 4 www.fairchildsemi.com ...
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... Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol T Free Air Ambient Temperature A V Supply Voltage CC ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 Parameter = 0V) CC Parameter 5 Rating –65°C to +150°C – ...
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... Current V Input Leakage Test ID I Output Leakage Circuit OD Current I Input LOW Current IL I Output Short-Circuit OS Current I Power Supply Voltage CC ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 V Conditions CC Recognized as a HIGH Signal Recognized as a LOW Signal = –18mA Min –1mA Min 20mA Min. ...
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... Propagation Delay, PLH PHL t Propagation Delay, PLH PHL t Propagation Delay, PLH PHL t Propagation Delay, PLH PHL ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0 +25° –55°C to +125° +5.0V +5.0V 50pF C = 50pF L L Min. Typ. Max. Min. 100 3.0 5.5 7.5 3 ...
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... S t (H) Hold Time, HIGH or LOW (L) PL Pulse Width LOW W t (L) CP Pulse Width LOW W t Recovery Time REC ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 = +25°C, = –55°C to +125° +5.0V = +5. Min. Max. Min. Max. 4.5 6.0 4.5 6.0 2.0 2 ...
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... Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 5. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 Package Number M16A 9 www.fairchildsemi.com ...
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... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 6. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 Package Number M16D 10 www.fairchildsemi.com ...
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... Physical Dimensions (Continued) Dimensions are in inches (millimeters) unless otherwise noted. Figure 7. 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide ©1988 Fairchild Semiconductor Corporation 74F191 Rev. 1.0.2 Package Number N16E 11 www.fairchildsemi.com ...
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... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ® ACEx Across the board. Around the world. ActiveArray Bottomless Build it Now CoolFET CROSSVOLT CTL™ Current Transfer Logic™ ...