TDA8798HL Philips Semiconductors, TDA8798HL Datasheet - Page 17

• Manufacturer Part Number: TDA8798HL
• Description: Dual 8-bit/ 100 Msps A/D converter with DPGA
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Note
1. When using the Track-and-Hold mode by setting TE LOW, the CLK input must never be HIGH for more than
2001 Feb 14
C
V
R
I
C
Serial Interface
D
V
V
I
I
G
f
t
t
t
t
t
t
t
t
t
o(ref)
IH
IL
SCLK(max)
W(SCLKH)
W(SCLKL)
su(SEN-SCLK)
h(SEN-SCLK)
su(SDATA-SCLK)
h(SMODE-SCLK)
h(SMODE-SEN)
d(SEN-Q)
d(SCLK-Q)
o(ref)
IL
IH
OMMON MODE REFERENCE OUTPUTS
o(ref)
o(ref)
IGITAL INPUTS
Dual 8-bit, 100 Msps A/D converter with optional DPGA
AIN CONTROL DATA TIMING
SYMBOL
t
t
for at least 50 ns. By using the application diagram clock input interface, see Fig. 17, the clock is guaranteed to
respect the t
W(CLKH)(max)
W(CLKH)(max)
(SEN1, SEN2, SCLK, SDATA
W(CLKH)(max)
reference output voltage
reference output resistance
reference maximum output
current
reference output capacitance
LOW-level input voltage
HIGH-level input voltage
HIGH-level input current
LOW-level input current
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
SEN to SCLK set-up time
SEN to SCLK hold time
SDATA to SCLK set-up time
SMODE to SCLK hold time
SMODE to SEN hold time
delay SEN rising edge to
change gain control register
value
delay SCLK rising edge to
change gain control register
value
even at power up to guarantee that the Track-and-Hold will start well. If CLK is set HIGH for more than
then, to correctly restart the Track-and-Hold, either TE has to be set LOW or CLK has to be set LOW
PARAMETER
(see Fig.5)
timing in all conditions, i.e. at start-up or if the clock is temporarily lost.
(V
OREF
1
AND
AND
at V
at V
V
SMODE)
OREF
CONDITIONS
o(cm)(ref)
o(cm)(ref)
2
)
17
0.2 V
V
100
0
2.0
20
20
20
8
5
5
5
10
5
5
DDA
MIN.
0.6
V
630
160
0
0
DDA
TYP.
0.5 V
3
0.8
V
+5
+5
5
5
Product specification
DDA
DDD
MAX.
TDA8798
0.4
V
pF
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
A
A
A