SG1625 National Semiconductor Corporation, SG1625 Datasheet - Page 6

• Manufacturer Part Number: SG1625
• Description: DS0026 - 5 MHZ Two Phase MOS Clock Driver Life-time Buy , Package: Soic Narrow, Pin Nb=8
• Manufacturer: National Semiconductor Corporation

www.national.com
Application Hints
Line ringing comes from the fact that at a high enough
frequency any line must be considered as a transmission
line with distributed inductance and capacitance. To see how
much ringing can be tolerated we must examine the clock
voltage specification. Figure 3 shows the clock specification,
in diagram form, with idealized ringing sketched in. The
ringing of the clock about the V
If the V
information stored in the memory could be altered. Referring
to Figure 1 , if the threshold voltage of a transistor were
−1.3V, the clock going to V
devices, whose gates are tied to that clock, would be only
300 mV from turning on. The internal circuitry needs this
noise margin and from the functional description of the RAM
it is easy to see that turning a clock on at the wrong time can
have disastrous results.
Controlling the clock ringing is particularly difficult because of
the relative magnitude of the allowable ringing, compared to
magnitude of the transition. In this case it is 1V out of 20V or
only 5%. Ringing can be controlled by damping the clock
driver and minimizing the line inductance.
Damping the clock driver by placing a resistance in series
with its output is effective, but there is a limit since it also
slows down the rise and fall time of the clock signal. Because
the typical clock driver can be much faster than the worst
case driver, the damping resistor serves the useful function
of limiting the minimum rise and fall time. This is very impor-
tant because the faster the rise and fall times, the worse the
ringing problem becomes. The size of the damping resistor
varies because it is dependent on the details of the actual
application. It must be determined empirically. In practice a
resistance of 10
Limiting the inductance of the clock lines can be accom-
plished by minimizing their length and by laying out the lines
such that the return current is closely coupled to the clock
lines. When minimizing the length of clock lines it is impor-
tant to minimize the distance from the clock driver output to
the furthest point being driven. Because of this, memory
boards are usually designed with clock drivers in the center
of the memory array, rather than on one side, reducing the
maximum distance by a factor of 2.
Using multilayer printed circuit boards with clock lines sand-
wiched between the V
the inductance of the clock lines. It also serves the function
of preventing the clocks from coupling noise into input and
output lines. Unfortunately multilayer printed circuit boards
SS
− 1 V
FIGURE 3. Clock Waveform
OH
to 20
is not maintained, at all times, the
DD
is usually optimum.
and V
SS
SS
− 1 would mean that all the
(Continued)
SS
level is particularly critical.
power plains minimizes
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are more expensive than two sided boards. The user must
make the decision as to the necessity of multilayer boards.
Suffice it to say here, that reliable memory boards can be
designed using two sided printed circuit boards.
Because of the amount of current that the clock driver must
supply to its capacitive load, the distribution of power to the
clock driver must be considered. Figure 4 gives the idealized
voltage and current waveforms for a clock driver driving a
1000 pF capacitor with 20 ns rise and fall time.
As can be seen the current is significant. This current flows
in the V
the lines will produce large voltage transients on the power
supplies. A bypass capacitor, as close as possible to the
clock driver, is helpful in minimizing this problem. This by-
pass is most effective when connected between the V
V
the amount of capacitance being driven. Using a low induc-
tance capacitor, such as a ceramic or silver mica, is most
effective. Another helpful technique is to run the V
V
tends to reduce the lines inductance and therefore the mag-
nitude of the voltage transients.
While discussing the clock driver, it should be pointed out
that the DS0026 is a relatively low input impedance device.
It is possible to couple current noise into the input without
seeing a significant voltage. Since the noise is difficult to
detect with an oscilloscope it is often overlooked.
DD
SS
FIGURE 4. Clock Waveforms (Voltage and Current)
supplies. The size of the bypass capacitor depends on
lines, to the clock driver, adjacent to each other. This
DD
and V
SS
power lines. Any significant inductance in
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DD
SS
and
and