74F160APC Fairchild Semiconductor, 74F160APC Datasheet - Page 3

• Manufacturer Part Number: 74F160APC
• Description: IC COUNTER SYNC PRESET BCD 16DIP
• Manufacturer: Fairchild Semiconductor
• Series: 74Fr

Specifications of 74F160APC

• Logic Type: Counter, Decade
• Direction: Up
• Number Of Elements: 1
• Number Of Bits Per Element: 4
• Reset: Asynchronous
• Timing: Synchronous
• Count Rate: 120MHz
• Trigger Type: Positive Edge
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74F160

Functional Description
The 74F160A and 74F162A count modulo-10 in the BCD
(8421) sequence. From state 9 (HLLH) they increment to
state 0 (LLLL). The clock inputs of all flip-flops are driven in
parallel through a clock buffer. Thus all changes of the Q
outputs (except due to Master Reset of the (F160A) occur
as a result of, and synchronous with, the LOW-to-HIGH
transition of the CP input signal. The circuits have four fun-
damental modes of operation, in order of precedence:
asynchronous reset (F160A), synchronous reset (F162A),
parallel load, count-up and hold. Five control inputs—Mas-
ter Reset (MR, F160A), Synchronous Reset (SR, F162A),
Parallel Enable (PE), Count Enable Parallel (CEP) and
Count Enable Trickle (CET)—determine the mode of oper-
ation, as shown in the Mode Select Table. A LOW signal on
MR overrides all other inputs and asynchronously forces all
outputs LOW. A LOW signal on SR overrides counting and
parallel loading and allows all outputs to go LOW on the
next rising edge of CP. A LOW signal on PE overrides
counting and allows information on the Parallel Data (P
inputs to be loaded into the flip-flops on the next rising
edge of CP. With PE and MR (F160A) or SR (F162A)
HIGH, CEP and CET permit counting when both are HIGH.
Conversely, a LOW signal on either CEP or CET inhibits
counting.
Mode Select Table
*For 74’F162A only
H
L
X
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
*SR
LOW Voltage Level
HIGH Voltage Level
Immaterial
H
H
H
H
L
PE
X
H
H
H
L
CET CEP
X
X
H
X
L
X
X
H
X
L
Reset (Clear)
Load (P
Count (Increment)
No Change (Hold)
No Change (Hold)
Action on the Rising
Clock Edge (
n
Q
n
)

)
n
)
3
The F160A and F162A use D-type edge-triggered flip-flops
and changing the SR, PE, CEP and CET inputs when the
CP is in either state does not cause errors, provided that
the recommended setup and hold times, with respect to the
rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 9. To implement synchronous
multistage counters, the TC outputs can be used with the
CEP and CET inputs in two different ways. Please refer to
the F568 data sheet. The TC output is subject to decoding
spikes due to internal race conditions and is therefore not
recommended for use as a clock or asynchronous reset for
flip-flops, counters or registers. In the F160A and F162A
decade counters, the TC output is fully decoded and can
only be HIGH in state 9. If a decade counter is preset to an
illegal state, or assumes an illegal state when power is
applied, it will return to the normal sequence within two
counts, as shown in the State Diagram.
Logic Equations:
State Diagram
Count Enable
TC
CEP
Q
0
Q
CET
1
Q
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2
PE
Q
3
CET