TDA8030 Philips Semiconductors, TDA8030 Datasheet - Page 17

• Manufacturer Part Number: TDA8030
• Description: USB smart card reader (OTP or ROM)
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 8 Time-out counter configuration
The time-out counter is very useful for processing the clock
counting during ATR, the Work Waiting Time (WWT) or the
waiting times defined in T = 1 protocol. The 200 and
384 clock counter used during ATR is done by hardware
when Start Session is set, a specific hardware takes care
of BGT in T = 1 protocol and a specific register is present
for processing the extra guard time.
It is not allowed to change the content of the TOR registers
whilst a counter is in software triggered mode, or in
autoreload mode. In these modes, it is mandatory to stop
the counters (TOCR = 00H or 05H) before updating the
count value in the TOR registers. In start bit triggered
mode, the value may be changed at any time; the new
count value will be taken into account on the next start bit.
2003 Jul 04
TOC VALUE
USB smart card reader (OTP or ROM)
7CH
00H
05H
61H
65H
68H
85H
E5H
All counters are stopped.
Counters 2 and 3 are stopped; counter 1 continues to operate in autoreload mode.
Counter 1 is stopped and counters 3 and 2 form a 16-bit counter. Counting the value stored in TOR3
and TOR2 is started after 6H is written in the TOCR. An interrupt is given and bit TO3 is set within the
USR when the terminal count is reached. The counter is stopped by writing 00H in the TOCR and will
be stopped before reloading a new value in TOR2 and TOR3.
Counter 1 is an 8-bit autoreload counter and counters 3 and 2 form a 16-bit counter. Counter 1 starts
counting the content of TOR1 on the first START bit (reception or transmission) detected on I/O after
65H is written in the TOCR. When Counter 1 reaches its terminal count, an interrupt is given, bit TO1 in
the USR is set and the counter automatically restarts the same count until it is stopped. It is not allowed
to change the content of TOR1 during a count. Counters 3 and 2 are wired as a single 16-bit counter
and starts counting the value TOR3 and TOR2 when 65H is written in the TOCR. When the counter
reaches its terminal count, an interrupt is given and bit TO3 is set within the USR. Both counters are
stopped when 00H is written in the TOCR. Counters 3 and 2 will be stopped by writing 05H in the
TOCR before reloading a new value in TOR2 and TOR3.
Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in TOR3,
TOR2 and TOR1 is started after 68H is written in the TOCR. The counter is stopped by writing 00H in
the TOCR. It is not allowed to change the content of TOR3, TOR2 and TOR1 within a count.
Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in TOR3,
TOR2 and TOR1 on the first start bit detected on I/O (reception or transmission) after the value has
been written. It is possible to change the content of TOR3, TOR2 and TOR1 during a count; the current
count will not be affected and the new count value will be taken into account at the next start bit. The
counter is stopped by writing 00H in the TOCR. In this configuration TOR3, TOR2 and TOR1 must not
be all zero.
Same as 05H, except that all the counters will be stopped at the end of the 12th ETU following the first
received start bit detected after 85H has been written in the TOCR.
Same configuration as TOCR = 65H, except that Counter 1 will be stopped at the end of the 12th ETU
following the first start bit detected after E5H has been written in the TOCR.
OPERATING MODE
17
The minimum time interval between 2 successive write
operations in TOCR is
It is obvious that the counters may only be used once the
card has been activated.
Detailed examples of how to use these specific timers can
be found in Application Note “AN01012” .
2
31
TDA8030; TDA8031
or
2
32
ETU.
Product specification