TDA10085 Philips Semiconductors, TDA10085 Datasheet - Page 7

• Manufacturer Part Number: TDA10085
• Description: Single chip DVB-S/DSS channel receiver
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Notes
1. TTL, 5 V tolerant input (if VDDE5 is connected to 5 V).
2. DGND, VSSI and VSSE can be connected to the same ground plane.
2001 Aug 31
TDO
ADVD
ADVS
VDDE
VSSE
CLB#
PSYNC
UNCOR
DEN
OCLK
DO0
DO1
DO2
DO3
VDDI
VSSI
VDDE
VSSE
DO4
DO5
DO6
DO7
22K
VSSI
Single chip DVB-S/DSS channel receiver
SYMBOL
PIN
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
ground
ground
ground
ground
ground
supply
supply
supply
supply
TYPE
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
boundary scan mode: test data serial output; output provided on the
falling edge of TCK
serial mode enabled (ENSERI = 1): serial TS enable input; must be
set to VSS when not in serial mode
analog supply voltage for the 2nd PLL (typically 1.8 V)
analog ground voltage for the 2nd PLL
digital supply voltage (typically 3.3 V)
digital ground voltage; see note 2
asynchronous, active LOW input that clears the TDA10085; when
CLB# goes LOW the circuit immediately enters its RESET mode and
normal operation resumes three XIN rising edges later after CLB#
returns HIGH; at RESET, the I
initialized to their default values; the minimum width of CLB# LOW
level is three XIN clock periods; pin CLB# is not TTL, 5 V tolerant
packet sync output signal goes HIGH on a rising edge of OCLK each
time the first byte of a packet is provided
uncorrectable packet output signal goes HIGH on a rising edge of
OCLK when the packet provided is uncorrectable
data enable; this output signal is HIGH when there is valid data on
bus DO[7:0]
output clock for the parallel DO[7:0] outputs; OCLK is generated
internally and depends on which interface type is selected
transport stream data output bits; part of the 8-bit parallel data output
after demodulation, Viterbi decoding, de-interleaving, RS decoding
and de-scrambling; possible output interfaces are three parallel and
two serial
digital core supply voltage (typically 1.8 V)
digital core ground voltage; see note 2
digital supply voltage (typically 3.3 V)
digital ground voltage; see note 2
transport stream data output bits; part of the 8-bit parallel data output
after demodulation, Viterbi decoding, de-interleaving, RS decoding
and de-scrambling; possible output interfaces are three parallel and
two serial
22 kHz output used to control the antenna LNB (output is controlled
via the I
digital core ground voltage; see note 2
2
C-bus interface)
7
DESCRIPTION
2
C-bus register contents are all
TDA10085HT
Product specification