ICL7650S Intersil Corporation, ICL7650S Datasheet - Page 4

• Manufacturer Part Number: ICL7650S
• Description: Super Chopper-Stabilized Operational Amplifier
• Manufacturer: Intersil Corporation

forward-type injection into the compensation capacitor, which
Electrical Specifications
NOTES:
Test Circuit
Application Information
Detailed Description
AMPLIFIER
The functional diagram shows the major elements of the
ICL7650S. There are two amplifiers, the main amplifier, and the
nulling amplifier. Both have offset-null capability. The main
amplifier is connected continuously from the input to the output,
while the nulling amplifier, under the control of the chopping
oscillator and clock circuit, alternately nulls itself and the main
amplifier. The nulling connections, which are MOSFET gates,
are inherently high impedance, and two external capacitors
provide the required storage of the nulling potentials and the
necessary nulling-loop time constants. The nulling arrangement
operates over the full common-mode and power-supply
ranges, and is also independent of the output level, thus giving
exceptionally high CMRR, PSRR, and A
Careful balancing of the input switches, and the inherent
balance of the input circuit, minimizes chopper frequency
charge injection at the input terminals, and also the feed
is the main cause of output spikes in this type of circuit.
INTERMODULATION
Previous chopper-stabilized amplifiers have suffered from
intermodulation effects between the chopper frequency and
input signals. These arise because the finite AC gain of the
Output Sink Current
Internal Chopping Frequency
Clamp ON Current (Note 5)
Clamp OFF Current (Note 5)
3. These parameters are guaranteed by design and characterization, but not tested at temperature extremes because thermocouple effects prevent
4. OUTPUT CLAMP not connected. See typical characteristic curves for output swing vs clamp current characteristics.
5. See OUTPUT CLAMP under detailed description.
6. All significant improvements over the industry-standard ICL7650 are highlighted in bold italics.
precise measurement of these voltages in automatic test equipment.
PARAMETER
1MΩ
R
1
0.1µF
ICL7650S
+
-
1MΩ
C
R
2
C
4
R
V
SUPPLY
C
0.1µF
VOL
= ±5V. See Test Circuit, Unless Otherwise Specified (Continued)
OUTPUT
.
SYMBOL
I
O SINK
f
CH
Pins 13 and 14 Open
R
-4V ≤ V
L
TEST CONDITIONS
ICL7650S
= 100kΩ
OUT
≤ +4V
amplifier necessitates a small AC signal at the input. This is
seen by the zeroing circuit as an error signal, which is
chopped and fed back, thus injecting sum and difference
frequencies and causing disturbances to the gain and phase
vs frequency characteristics near the chopping frequency.
These effects are substantially reduced in the ICL7650S by
feeding the nulling circuit with a dynamic current,
corresponding to the compensation capacitor current, in such
a way as to cancel that portion of the input signal due to finite
AC gain. Since that is the major error contribution to the
ICL7650S, the intermodulation and gain/phase disturbances
are held to very low values, and can generally be ignored.
CAPACITOR CONNECTION
The null/storage capacitors should be connected to the
C
C
either a separate wire or PC trace to avoid injecting load
current IR drops into the capacitive circuitry. The outside foil,
where available, should be connected to C
OUTPUT CLAMP
The OUTPUT CLAMP pin allows reduction of the overload
recovery time inherent with chopper-stabilized amplifiers.
When tied to the inverting input pin, or summing junction, a
current path between this point and the OUTPUT pin occurs
just before the device output saturates. Thus uncontrolled
input differentials are avoided, together with the consequent
charge buildup on the correction-storage capacitors. The
output swing is slightly reduced.
CLOCK
The ICL7650S has an internal oscillator, giving a chopping
frequency of 200Hz, available at the CLOCK OUT pin on the 14
pin devices. Provision has also been made for the use of an
external clock in these parts. The INT/EXT pin has an internal
pull-up and may be left open for normal operation, but to utilize
an external clock this pin must be tied to V- to disable the
internal clock. The external clock signal may then be applied to
the EXT CLOCK IN pin. An internal divide-by-two provides the
EXTA
RETN
and C
pin. This connection should be made directly by
TEMP.
0 to 70
0 to 70
EXTB
(
o
25
25
25
25
C)
pins, with a common connection to the
MIN
120
25
20
25
-
-
0.001
TYP
250
30
70
-
-
RETN
MAX
375
10
5
-
-
-
.
UNITS
mA
mA
Hz
µA
nA
nA