IDT72T51336 ETC-unknow, IDT72T51336 Datasheet
IDT72T51336
Related parts for IDT72T51336
IDT72T51336 Summary of contents
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... User programmable via serial port • • • • • Default multi-queue device configurations -IDT72T51336: 2,048 -IDT72T51346: 4,096 -IDT72T51356: 8,192 • • • • • 100% Bus Utilization, Read and Write on every clock cycle • ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits DESCRIPTION: The IDT72T51336/72T51346/72T51356 multi-queue flow-control de- vices are single chip within which anywhere between 1 and 8 discrete FIFO queues can be setup. All queues within the device have a common data input bus, (write port) and a common data output bus, (read port) ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits WCLK WEN 6 WRADD Write Control Logic WADEN Write Pointers PAF FSTR 8 General Flag PAFn Monitor FSYNC FXO FXI FF Active Q Flags PAF SI SO Serial SCLK Multi-Queue Programming SENI SENO ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN CONFIGURATION A1 BALL PAD CORNER A D14 D13 D12 D10 B D15 D16 D11 D9 C D17 D18 D19 D8 D D20 D21 D22 V DDQ E D23 D24 D25 V DDQ F D26 D27 D28 ...
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... Also the total size of any given queue must be in increments of 256 x36. For the IDT72T51336/ 72T51346 and IDT72T51356 the Total Available Memory is 64, 128 and 256 blocks respectively (a block being 256 x36) ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits EXPANSION Expansion of multi-queue devices is also possible devices can be connected in a parallel fashion providing the possibility of both depth expansion or queue expansion. Depth Expansion means expanding the depths of individual queues. Queue expansion means increasing the total number of queues available ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS Symbol & Name I/O TYPE Pin No. BM Bus Matching LVTTL (L14) INPUT D[35:0] Data Input Bus HSTL-LVTTL These are the 36 data input pins. Data is written into the device via these input pins on the rising edge ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. PAFn Flag Bus FSTR LVTTL (R4) Strobe INPUT PAFn Bus Sync FSYNC LVTTL (R3) OUTPUT PAFn Bus FXI LVTTL (T2) Expansion In INPUT PAFn Bus ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. OV Output Valid HSTL-LVTTL This output flag provides output valid status for the data word present on the multi-queue flow-control device ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. PRS Partial Reset HSTL-LVTTL A Partial Reset can be performed on a single queue selected within the multi-queue device. Before a Partial (T8) INPUT Q[35:0] Data Output Bus HSTL-LVTTL These are the 36 data output pins. Data is read out of the device via these output pins on the rising edge ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. SENI HSTL-LVTTL to be programmed (SENO will follow SENI of a given device once that device is programmed). The SENI Serial Input (Continued) ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. WEN HSTL-LVTTL The WEN input enables write operations to a selected queue based on a rising edge of WCLK. A queue Write Enable (T6) ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage Temperature STG I DC Output Current OUT NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits DC ELECTRICAL CHARACTERISTICS (Commercial 2.5V ± 0.125V 0°C to +70°C;Industrial Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO (3) V Output Logic “1” Voltage ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits HSTL 1.5V AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels NOTE 1.5V±. DDQ EXTENDED HSTL 1.8V AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits AC ELECTRICAL CHARACTERISTICS (Commercial 2.5V ± 0.15V 0°C to +70°C;Industrial Symbol Parameter f Clock Cycle Frequency (WCLK & RCLK Data Access Time A t Clock Cycle Time CLK ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits AC ELECTRICAL CHARACTERISTICS (CONTINUED) (Commercial 2.5V ± 0.15V 0°C to +70°C;Industrial Symbol Parameter t Read Clock to Synchronous Almost-Empty Flag Bus PAE t RCLK to Echo RCLK Output ERCLK RCLK to Echo REN Output ...
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... PAE/PAF offset values. The IDT72T51336/72T51346/72T51356 devices are capable queues and therefore contain 8 sets of registers for the setup of each queue. During a Master Reset if the DFM (Default Mode) input is LOW, then the device will require serial programming by the user recommended that the user utilize a ‘ ...
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... STANDARD MODE OPERATION (PKT = LOW ON MASTER RESET) WRITE QUEUE SELECTION AND WRITE OPERATION (STANDARD MODE) The IDT72T51336/72T51346/72T51356 multi-queue flow-control devices can be configured maximum of 8 queues into which data can be written via a common write port using the data inputs (Din), write clock (WCLK) and write enable (WEN) ...
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... QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits READ QUEUE SELECTION AND READ OPERATION (STANDARD MODE) The IDT72T51336/72T51346/72T51356 multi-queue flow-control devices can be configured maximum of 8 queues which data can be read via a common read port using the data outputs (Qout), read clock (RCLK) and read enable (REN) ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits WRITE QUEUE SELECTION AND WRITE OPERATION (PACKET MODE required that a full packet be written to a queue before moving to a different queue. The device requires three cycles to change queues. Packet mode, has 2 restrictions: < ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits TABLE 5 — PACKET MODE VALID BYTE TMOD1 (D33) RMOD1 (Q33) NOTE: Packet Mode is only available when the Input Port and Output Port are 36 bits wide. the queue, regardless of REN. For example TSOP has been written and some number of words later a TEOP is written a full packet of data is deemed to be available, and the PR flag and OV will go active LOW ...
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... Figure 21, Read Operation and Null Queue Select for diagram. PAFn FLAG BUS OPERATION The IDT72T51336/72T51346/72T51356 Multi-queue flow-control devices can be configured for queues, each queue having its own almost full status. An active queue has its flag status output to the discrete flags, FF and PAF, on the write port ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits newly selected queue. On the third rising edge of WCLK following the queue selection, data can be written into the newly selected queue provided that data and enable setup & hold times are met. ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits of the default values (8 or 128) can be selected if the user has performed default programming. As mentioned, every queue within a multi-queue device has its own almost full status, when a queue is selected on the write port, this status is output via the PAF flag ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING Output Valid, OV Flag Boundary I/O Set-Up OV Goes LOW after 1 In36 to out36 (Almost Empty Mode) (Both ports selected for same queue (see note 1 below for timing) ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED) Programmable Almost Empty Flag, PAE Boundary I/O Set-Up in36 to out36 (Both ports selected for same queue when the 1 Word is written in until the boundary is reached) ...
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... Please refer to Figure 30, PAF n Bus – Polled Mode for timing information. PAEn/PRn FLAG BUS OPERATION The IDT72T51336/72T51346/72T51356 multi-queue flow-control devices can be configured for queues, each queue having its own almost empty/ packet ready status. An active queue has its flag status output to the discrete flags, OV, PAE and PR, on the read port ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits ECHO READ CLOCK (ERCLK) The Echo Read Clock output is provided in both HSTL and LVTTL mode, selectable via IOSEL. The ERCLK is a free-running clock output, it will always follow the RCLK input regardless of REN and RADEN. ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT BYTE ORDER ON INPUT PORT: ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits MRS t RSS WEN REN t RSS SENI t RSS FSTR, ESTR t RSS WADEN, RADEN t RSS ID0, ID1, ID2 t RSS OW, IW RSS FM t RSS MAST t RSS PKT t RSS DFM t RSS ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits w-3 WCLK WADEN WEN WRADD Qx FF PAF Active Bus PAF-Qx (5) PRS RCLK REN RADEN t AS RDADD Qx OV PAE Active Bus PAE-Qx (6) r-2 NOTES: 1. For a Partial Reset to be performed on a Queue, that Queue must be selected on both the write and read ports. ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 33 TEMPERATURE RANGES ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 34 TEMPERATURE RANGES ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 35 TEMPERATURE RANGES ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits WCLK t ENS WEN RCLK REN Qout Last Word Read Out of Queue OV NOTES has previously been selected on both the write and read ports LOW. ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 37 TEMPERATURE RANGES ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 38 TEMPERATURE RANGES ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* *B* RCLK t ENS REN RDADD Addr=001011 RADEN Qout (Device 1) OV HIGH-Z (Device 1) OV (Device 2) WCLK WEN WRADD WADEN Din Cycle: *A* Queue 3 of Device 1 is selected for read operations. The OV is currently being driven by Device 2, a queue within device 2 is selected for reads. Device 2 also has control of Qout bus, its Qout outputs are in Low-Impedance ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 40 TEMPERATURE RANGES ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 41 TEMPERATURE RANGES ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 42 TEMPERATURE RANGES ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 43 TEMPERATURE RANGES ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 44 TEMPERATURE RANGES ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 45 TEMPERATURE RANGES ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits NULL QUEUE SELECT *A* RCLK t AS Don’t care RDADD t QS RADEN t AS Null-Q REN t A Qout Q1 Wn-4 Q1 Wn-3 OV NOTES: 1. The purpose of the Null queue operation is so that the user can stop reading a block (packet) of data from a queue without filling the 2 stage output pipeline with the next words from that queue ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* *B* WCLK WEN WRADD Addr=001010 WADEN Din PAF HIGH-Z (Device 1) PAF (Device 2) Cycle: *A* Queue 2 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The PAF output of device 1 is High-Impedance. ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* *B* RCLK REN HIGH RDADD Addr=001011 RADEN HIGH-Z Qout PAE HIGH-Z (Device 1) PAE (Device 2) Cycle: *A* Queue 3 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The PAE flag output and the data outputs of device 1 are High-Impedance. ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 49 TEMPERATURE RANGES ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* WCLK WADEN FSTR t ENS WEN WRADD D5Q3 t 100 011 DS Wp Wp+1 Dn Writes to Previous Q RCLK RADEN ESTR REN RDADD D5Q3 100 011 ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* *B* RCLK RADEN ESTR REN RDADD D0Q1 000 001 OE t OLZ Qout W X Prev. Q WCLK t t STS STH FSTR WRADD Device 0 ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits WCLK FSYNC 0 (MASTER) FXO 0 / FXI 1 FSYNC 1 (SLAVE) FXO 1 / FXI 2 FSYNC 2 (SLAVE) FXO 2 / FXI 0 PAF[7:0] NOTE: 1. This diagram is based on 3 devices connected to expansion mode FSYNC FSYNC t t FXO ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits RCLK ESYNC 0 EXO 0 / EXI 1 ESYNC 1 EXO 1 / FXI 2 ESYNC 2 EXO 2 / EXI 0 PAE ESYNC ESYNC t t EXO EXO t ESYNC t EXO t ESYNC t EXO t t PAE PAE Device 0 Device 1 Figure 31. PAE Bus - Polled Mode ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits WCLK WEN D[39:0] D10 D11 RCLK REN Q[39: ERCLK ERCLK EREN NOTES: 1. All read and write operations must have ceased a minimum of 4 WCLK and 4 RCLK cycles before power down is asserted. ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits Serial Programming Data Input Serial Enable Data Bus Write Clock Write Enable Write Queue Select Write Address Full Strobe Programmable Almost Full Full Sync1 Full Flag Almost Full Flag ...
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... QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits JTAG INTERFACE Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72T51336/72T51346/ 72T51356 incorporates the necessary tap controller and modified pad cells to implement the JTAG facility. ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits 1 0 Input = TMS NOTES: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. 2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS). ...
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... TAP in response to the IDCODE instruction. IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is dropped in the 11-bit Manufacturer ID field. For the IDT72T51336/72T51346/72T51356, the Part Number field con- tains the following values: Device Part# Field (HEX) ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits HIGH-IMPEDANCE The optional High-Impedance instruction sets all outputs (including two-state as well as three-state types disabled (high-impedance) state and selects the one-bit bypass register to be connected between TDI and TDO. ...
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... IDT72T51336/72T51346/72T51356 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits t 1 TCK t 3 TDI/ TMS TDO t 6 TRST t 5 SYSTEM INTERFACE PARAMETERS Parameter Symbol Test Conditions Data Output t (1) DO Data Output Hold t (1) DOH Data Input rise=3ns ...
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ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range product for 6ns speed grade is available as a standard device. All other speed grades available by special order. DATASHEET DOCUMENT HISTORY 08/19/2003 pgs. 1 ...