SI3460 Silicon Laboratories, SI3460 Datasheet - Page 9

• Manufacturer Part Number: SI3460
• Description: IEEE 802.3af PSE INTERFACE AND DC-DC CONTROLLER
• Manufacturer: Silicon Laboratories

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4.1. PSE Timing Characteristics
When implemented in accordance with the recommended external components and layout guidelines, the Si3460
controller enables the following typical performance characteristics in single-port PSE applications. Refer to the
Si3460-EVB applications note, schematics, and user's guide for more details.
4.1.1. PSE Timing Diagrams
The basic sequence of applying power is shown in Figure 3. Following is the description of the function that must
be performed in each phase.
Endpoint detection delay
cycle
Detection time
Classification delay cycle
Classification time
Power-up turn-on delay
Midspan detect backoff time
Current limit time
Disconnect delay
*Note: These typical specifications are based on an ambient operating temperature of 25 ºC and V
Description
Figure 3. Detection, Classification, Powerup, and Disconnect Sequence
20.5 V
15.5 V
2.8 V
57 V
10 V
44 V
t
CLASS_CYCLE
t
DET_CYCLE
t
Symbol
t
DET_CYCLE
t
t
DETECT
t
PWRUP
DC_DIS
CLASS
t
t
BOM
LIM
Table 6. PSE Timing*
Time from when a valid detection is
Time from PD connection to port to
Time from successful detect mode
Time required to measure PD sig-
Preliminary Rev. 0.4
completion of detection process.
completed until V
t
CLASS_CYCLE
to classification complete.
nature resistance.
Test Conditions
t
PWRUP
applied
OUT
power is
Min
70
10
10
2
IN
Typ
350
= +12 V.
70
30
60
(msec)
Time
Si3460
Max
400
50
50
Unit
ms
ms
ms
ms
ms
ms
ms
s
9
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