AAT2510IWP-AA-T1 AnalogicTech, AAT2510IWP-AA-T1 Datasheet - Page 13
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AAT2510IWP-AA-T1
Manufacturer Part Number
AAT2510IWP-AA-T1
Description
Dual 400mA, 1MHz Step-Down DC-DC Converter
Manufacturer
AnalogicTech
Datasheet
1.AAT2510IWP-AA-T1.pdf
(20 pages)
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Quantity
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Part Number:
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Thermal Calculations
There are three types of losses associated with the
AAT2510 converter: switching losses, conduction
losses, and quiescent current losses. Conduction
losses are associated with the R
of the power output switching devices. Switching
losses are dominated by the gate charge of the
power output switching devices. At full load, assum-
ing continuous conduction mode (CCM), a simplified
form of the dual converter losses is given by:
I
nel and t
ing losses.
For the condition where channel one is in dropout
at 100% duty cycle, the total device dissipation
reduces to:
Since R
losses all vary with input voltage, the total losses
should be investigated over the complete input
voltage range.
2510.2005.08.1.5
P
P
Q
TOTAL
TOTAL
is the AAT2510 quiescent current for one chan-
+
+ (t
+
+ (t
= I
=
DS(ON)
sw
I
I
I
O1
O1
O2
O2
sw
sw
2
2
2
2
is used to estimate the full load switch-
· F · I
· F · [I
· R
· (R
· (R
· (R
, quiescent current, and switching
DSON(HS)
DSON(HS)
DSON(HS)
DSON(HS)
O2
O1
+ 2 · I
+ I
O2
· V
· V
· V
] + 2 · I
Q
O2
O1
O2
) · V
V
V
+ R
+ R
V
+ R
IN
IN
IN
IN
DS(ON)
Q
DSON(LS)
DSON(LS)
DSON(LS)
) · V
IN
characteristics
Dual 400mA, 1MHz Step-Down DC-DC Converter
· [V
· [V
· [V
IN
IN
IN
-V
-V
-V
O1
O2
O2
])
])
])
Given the total losses, the maximum junction tem-
perature can be derived from the θ
TDFN33-12 package which is 50°C/W.
PCB Layout
The following guidelines should be used to insure a
proper layout.
1. Due to the pin placement of V
2. The output capacitor and inductor should be
3. The feedback trace should be separate from any
4. The resistance of the trace from the load return
5. For good thermal coupling, PCB vias are required
verters, proper decoupling is not possible with
just one input capacitor. The large input capaci-
tor C3 should connect as closely as possible to
V
tional input bypass capacitor C8 is necessary for
proper high frequency decoupling of the second
converter.
connected as closely as possible. The connec-
tion of the inductor to the LX pin should also be
as short as possible.
power trace and connect as closely as possible
to the load point. Sensing along a high-current
load trace will degrade DC load regulation. If
external feedback resistors are used, they
should be placed as closely as possible to the
FB pin. This prevents noise from being coupled
into the high impedance feedback node.
to GND should be kept to a minimum. This will
help to minimize any error in DC regulation due
to differences in the potential of the internal sig-
nal ground and the power ground.
from the pad for the TDFN paddle to the ground
plane. The via diameter should be 0.3mm to
0.33mm and positioned on a 1.2 mm grid.
P
and GND, as shown in Figure 4. The addi-
T
J(MAX)
= P
TOTAL
• Θ
JA
+ T
AAT2510
IN
AMB
for both con-
JA
for the
13