IDT71V2556S Integrated Device Technology, IDT71V2556S Datasheet - Page 18

• Manufacturer Part Number: IDT71V2556S
• Description: 128k X 36, 256k X 18 3.3v Synchronous Zbt Srams 2.5v I/o, Burst Counter Pipelined Outputs
• Manufacturer: Integrated Device Technology

NOTES:
1. D (A
2. CE
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before
the base address A
loaded into the SRAM.
the actual data is presented to the SRAM.
2
timing transitions are identical but inverted to the CE
1
) represents the first input to the external address A
2
, etc. where address bits A
0
and A
1
are advancing for the four word burst in the sequence defined by the state of the LBO input.
1
and CE
1
. D (A
2
2
) represents the first input to the external address A
signals. For example, when CE
1
and CE
2
are LOW on this waveform, CE2 is HIGH.
2
; D (A
2+1
) represents the next input data in the burst sequence of