IDT72413 Integrated Device Technology, IDT72413 Datasheet - Page 6

• Manufacturer Part Number: IDT72413
• Description: Cmos Parallel 64 X 5-bit Fifo With Flags
• Manufacturer: Integrated Device Technology

NOTES:
1. FIFO is initially full.
2. SO pulse is applied.
3. SI is held HIGH.
4. As soon as IR becomes HIGH the Input Data is loaded into the FIFO.
5. The write pointer is incremented. SI should not go LOW until (t
NOTES:
1. This data is loaded consecutively A, B, C.
2. Output data changes on the falling edge of SO after a valid SO sequence, i.e., OR and SO are both HIGH together.
NOTES:
1. OR HIGH indicates that data is available and a SO pulse may be applied.
2. SO goes HIGH causing the next step.
3. OR goes LOW.
4. Read pointer is incremented.
5. OR goes HIGH indicating that new data (B) will be available at the FIFO outputs after t
6. If the FIFO has only one word loaded (A DATA) , OR stays LOW and the A-DATA remains unchanged at the outputs.
7. SO pulses applied when OR is LOW will be ignored.
IDT72413 CMOS PARALLEL FIFO WITH FLAGS
64 x 5
OUTPUT DATA
OUTPUT DATA
INPUT DATA
SO
OR
IR
SO
SI
OR
SO
(7)
(1)
(1)
(1)
(2)
Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH
t
(2)
SOH
A-DATA
Figure 6. The Mechanism of Shifting Data Out of the FIFO
(3)
1/f
OUT
t
A- DATA
ODH
PT
t
+ tI
ODS
t
SOL
PH
Figure 5. Output TIming
(3)
t
).
ORD
t
PT
6
ORD
ns.
t
ORL
B-DATA
(2)
(4)
1/f
(4)
OUT
t
RH
STABLE DATA
COMMERCIAL TEMPERATURE RANGE
A or B
t
IPH
(5)
C-DATA
B- DATA
(6)
(5)
2748 drw 06
2748 drw 07
2748 drw 08