IDT72T51546 Integrated Device Technology, IDT72T51546 Datasheet - Page 2

• Manufacturer Part Number: IDT72T51546
• Description: 2.5v Multi-queue Flow-control Devices 32 Queues 36 Bit Wide Configuration 1,179,648 Bits And 2,359,296 Bits
• Manufacturer: Integrated Device Technology

DESCRIPTION:
chip within which anywhere between 1 and 32 discrete FIFO queues can be
setup. All queues within the device have a common data input bus, (write port)
and a common data output bus, (read port). Data written into the write port is
directed to a respective queue via an internal de-multiplex operation, ad-
dressed by the user. Data read from the read port is accessed from a respective
queue via an internal multiplex operation, addressed by the user. Data writes
and reads can be performed at high speeds up to 200MHz, with access times
of 3.6ns. Data write and read operations are totally independent of each other,
a queue maybe selected on the write port and a different queue on the read
port or both ports may select the same queue simultaneously.
selected for write and read operations respectively. Also a Programmable
Almost Full and Programmable Almost Empty flag for each queue is provided.
Two 8 bit programmable flag busses are available, providing status of queues
not selected for write or read operations. When 8 or less queues are configured
in the device these flag busses provide an individual flag per queue, when
more than 8 queues are used, either a Polled or Direct mode of bus operation
provides the flag busses with all queues status.
or 36 bits wide provided that at least one port is 36 bits wide. When Bus Matching
is used the device ensures the logical transfer of data throughput in a Little
Endian manner.
for 36 bit input and 36 bit output port sizes. The Packet mode provides the user
with a flag output indicating when at least one (or more) packets of data within
a queue is available for reading. The Packet Ready provides the user with
a means by which to mark the start and end of packets of data being passed
through the queues. The multi-queue device then provides the user with an
internally generated packet ready status per queue.
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
The IDT72T51546/72T51556 multi-queue flow-control devices is a single
The device provides Full flag and Output Valid flag status for the queue
Bus Matching is available on this device, either port can be 9 bits, 18 bits
A packet mode of operation is also provided when the device is configured
2
to program the total number of queues between 1 and 32, the individual queue
depths being independent of each other. The programmable flag positions are
also user programmable. All programming is done via a dedicated serial port.
If the user does not wish to program the multi-queue device, a default option is
available that configures the device in a predetermined manner.
Reset latches in all configuration setup pins and must be performed before
programming of the device can take place. A Partial Reset will reset the read and
write pointers of an individual queue, provided that the queue is selected on both
the write port and read port at the time of partial reset.
provided. These are outputs from the read port of the Queue that are required
for high speed data communication, to provide tighter synchronization between
the data being transmitted from the Qn outputs and the data being received by
the input device. Data read from the read port is available on the output bus with
respect to EREN and ERCLK, this is very useful when data is being read at high
speed.
either 2.5V LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of IO is selected
via the IOSEL input. The core supply voltage (V
2.5V, however the output levels can be set independently via a separate supply,
V
This input disables the write port data inputs when no write operations are
required.
fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture.
of the functional blocks within the device.
DDQ
The user has full flexibility configuring queues within the device, being able
Both Master Reset and Partial Reset pins are provided on this device. A Master
Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are
The multi-queue flow-control device has the capability of operating its IO in
The devices also provide additional power savings via a Power Down Input.
A JTAG test port is provided, here the multi-queue flow-control device has a
See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an outline
.
COMMERCIAL AND INDUSTRIAL
CC
TEMPERATURE RANGES
) to the multi-queue is always