IDT72V3650 Integrated Device Technology, IDT72V3650 Datasheet - Page 16

• Manufacturer Part Number: IDT72V3650
• Description: 2k X 36 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
D/Q35
D/Q35
D/Q17
1st Parallel Offset Write/Read Cycle
D/Q17
2nd Parallel Offset Write/Read Cycle
D/Q16
16
D/Q16
IDT72V3640/50/60/70/80/90 ⎯
16
16
15
16
15
IDT72V3640/50/60/70/80/90 ⎯ x36 Bus Width
15
14
D/Q19
D/Q19
EMPTY OFFSET (LSB) REGISTER (PAE)
15
14
FULL OFFSET (LSB) REGISTER (PAF)
14
13
17
17
14
13
D/Q17
13
D/Q17
12
13
12
Data Inputs/Outputs
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
11
12
17
16
17
16
Data Inputs/Outputs
EMPTY OFFSET REGISTER (PAE)
12
11
11
10
FULL OFFSET REGISTER (PAF)
16
15
16
15
11
10
10
15
14
15
14
9
10
D/Q8
9
14
13
14
13
9
D/Q8
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
9
13
13
12
12
8
8
8
8
11
12
11
12
7
7
7
7
11
10
6
11
10
6
# of Bits Used
6
6
10
10
5
5
9
9
D/Q8
5
5
D/Q8
4
4
9
9
x18 Bus Width
4
4
3
3
8
8
8
8
3
3
2
2
7
7
7
7
# of Bits Used
# of Bits Used
D/Q0
2
2
1
1
6
6
6
6
D/Q0
1
1
5
5
5
5
Interspersed
Parity
Non-Interspersed
Parity
4
4
4
4
3
3
3
3
2
2
2
2
TM
D/Q0
D/Q0
1
1
1
16
1
36-BIT FIFO
Non-Interspersed
Parity
Interspersed
Parity
Non-Interspersed
Parity
Interspersed
Parity
IDT72V3640/50/60/70/80/90 ⎯
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
D/Q8
D/Q8
D/Q8
D/Q8
16
8
8
EMPTY OFFSET REGISTER (PAE)
EMPTY OFFSET REGISTER (PAE)
FULL OFFSET REGISTER (PAF)
FULL OFFSET REGISTER (PAF)
15
15
7
7
14
14
6
6
COMMERCIAL AND INDUSTRIAL
# of Bits Used:
10 bits for the IDT72V3640
11 bits for the IDT72V3650
12 bits for the IDT72V3660
13 bits for the IDT72V3670
14 bits for the IDT72V3680
15 bits for the IDT72V3690
Note: All unused bits of the
LSB & MSB are don't care
13
13
5
5
TEMPERATURE RANGES
12
12
4
4
x9 Bus Width
11
11
3
3
APRIL 6, 2006
10
10
2
2
D/Q0
D/Q0
D/Q0
D/Q0
9
9
1
1
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