IDT74VC16244A Integrated Device Technology, IDT74VC16244A Datasheet - Page 5

• Manufacturer Part Number: IDT74VC16244A
• Description: 3.3v Cmos 16-bit Buffer/driver With 3-state Outputs, 5 Volt Tolerant I/o
• Manufacturer: Integrated Device Technology

TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
NOTES:
1. Pulse Generator for All Pulses: Rate  10MHz; t
2. Pulse Generator for All Pulses: Rate  10MHz; t
SWITCH POSITION
NOTES:
1.
2.
DEFINITIONS:
C
R
IDT74LVC16244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
L
T
Symbol
Generator
V
= Termination resistance: should be equal to Z
= Load capacitance: includes jig and probe capacitance.
V
For t
V
For t
LOAD
V
V
C
Pulse
HZ
LZ
IH
T
L
OUTPUT 2
OUTPUT 1
SK
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
(o) OUTPUT1 and OUTPUT2 are any two outputs.
All Other Tests
(1, 2)
Disable High
INPUT
Disable Low
Enable High
Enable Low
Open Drain
V
CC
Test
(1)
= 3.3V±0.3V V
V
300
300
2.7
1.5
50
6
IN
Test Circuit for All Outputs
t
SK
(x)
Output Skew - t
R
= t
T
t
D.U.T.
PLH1
V
PLH2
CC
CC
t
PLH2
(1)
300
300
2.7
1.5
50
6
t
-
= 2.7V
SK
t
PLH1
V
(x)
OUT
OUT
SK
F
F
or
t
(
 2ns; t
 2.5ns; t
PHL1
X
V
of the Pulse Generator.
t
)
CC
C
PHL2
t
PHL2
L
(2)
2 x Vcc
Switch
Vcc / 2
= 2.5V±0.2V
R
V
t
GND
Open
-
SK
Vcc
150
150
LOAD
30
R
 2ns.
t
PHL1
500
500
 2.5ns.
(x)
LVC Link
LVC Link
V
V
0V
V
V
V
V
V
V
IH
T
OH
T
OL
OH
T
OL
V
Open
GND
Unit
LOAD
mV
mV
pF
V
V
V
5
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
ASYNCHRONOUS
SYNCHRONOUS
INPUT TRANSITION
INPUT TRANSITION
OPPOSITE PHASE
NORMALLY
NORMALLY
HIGH-LOW-HIGH
CONTROL
CONTROL
LOW-HIGH-LOW
CONTROL
SAME PHASE
OUTPUT
OUTPUT
TIMING
INPUT
INPUT
DATA
INPUT
HIGH
OUTPUT
LOW
Set-up, Hold, and Release Times
PULSE
PULSE
Enable and Disable Times
CLOSED
SWITCH
SWITCH
ENABLE
OPEN
Propagation Delay
t
t
PZL
PZH
Pulse Width
t
t
PLH
PLH
INDUSTRIAL TEMPERATURE RANGE
t
SU
t
SU
V
V
0V
V
T
T
LOAD/2
t
W
t
REM
t
H
t
PHZ
t
t
DISABLE
PHL
PHL
t
H
t
PLZ
LVC Link
LVC Link
V
V
LVC Link
T
T
LVC Link
V
V
0V
V
V
V
V
V
0V
V
V
0V
V
V
V
V
V
0V
OH
IH
T
T
OL
IH
T
IH
T
LOAD/2
OL+
OL
OH
OH-
V
V
0V
V
V
0V
V
V
0V
V
V
0V
IH
T
IH
T
IH
T
IH
T
V
V
HZ
LZ