IDT74LVCH16646A Integrated Device Technology, IDT74LVCH16646A Datasheet - Page 7

• Manufacturer Part Number: IDT74LVCH16646A
• Description: 3.3v Cmos 16-bit Bus Transceiver/register With 3-state Outputs 5 Volt Tolerant I/o And Bus-hold
• Manufacturer: Integrated Device Technology

TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; t
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; t
SWITCH POSITION
NOTES:
1.
2.
DEFINITIONS:
C
R
IDT74LVCH16646A
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
L
T
Symbol
V
= Termination resistance: should be equal to Z
= Load capacitance: includes jig and probe capacitance.
Generator
V
V
For t
For t
LOAD
V
V
C
HZ
LZ
IH
T
L
Pulse
OUTPUT 2
SK
SK
OUTPUT 1
(b) OUTPUT1 and OUTPUT2 are in the same bank.
(o) OUTPUT1 and OUTPUT2 are any two outputs.
All Other Tests
Disable High
Disable Low
Enable High
Enable Low
Open Drain
V
INPUT
(1, 2)
CC
Test
(1)
= 3.3V±0.3V V
300
300
2.7
1.5
V
50
6
IN
Test Circuit for All Outputs
t
SK
(x)
Output Skew - t
R
= t
T
t
D.U.T.
PLH1
V
PLH2
CC
CC
t
PLH2
(1)
300
300
2.7
1.5
50
6
= 2.7V
t
-
SK
t
PLH1
V
(x)
OUT
OUT
SK
F
F
or
(
≤ 2ns; t
t
≤ 2.5ns; t
PHL1
X
V
of the Pulse Generator.
)
t
CC
C
PHL2
t
PHL2
L
(2)
2 x Vcc
Switch
Vcc / 2
= 2.5V±0.2V
R
V
t
GND
Open
SK
-
Vcc
150
150
LOAD
30
R
≤ 2ns.
t
500Ω
PHL1
500Ω
≤ 2.5ns.
(x)
LVC Link
LVC Link
0V
V
V
V
V
V
V
V
V
T
T
T
IH
OL
OL
OH
OH
V
Open
GND
LOAD
Unit
mV
mV
pF
V
V
V
7
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
ASYNCHRONOUS
SYNCHRONOUS
INPUT TRANSITION
INPUT TRANSITION
OPPOSITE PHASE
NORMALLY
NORMALLY
HIGH-LOW-HIGH
CONTROL
CONTROL
LOW-HIGH-LOW
CONTROL
SAME PHASE
OUTPUT
OUTPUT
TIMING
INPUT
INPUT
DATA
INPUT
HIGH
LOW
OUTPUT
Set-up, Hold, and Release Times
PULSE
PULSE
CLOSED
SWITCH
SWITCH
Enable and Disable Times
ENABLE
OPEN
Propagation Delay
t
t
PZH
PZL
t
t
PLH
PLH
Pulse Width
INDUSTRIAL TEMPERATURE RANGE
t
SU
t
SU
V
0V
V
V
T
T
LOAD/2
t
W
t
REM
t
H
t
PHZ
t
t
DISABLE
PHL
PHL
t
H
t
PLZ
LVC Link
LVC Link
V
LVC Link
V
T
T
LVC Link
V
V
0V
V
V
V
V
V
0V
0V
V
V
V
V
V
V
0V
V
IH
T
OH
T
OL
IH
T
T
IH
LZ
OH
HZ
LOAD/2
OL
0V
0V
0V
0V
V
V
V
V
V
V
V
V
T
T
T
T
IH
IH
IH
IH