IDTCSPT857 Integrated Device Technology, IDTCSPT857 Datasheet - Page 6

no-image

IDTCSPT857

Manufacturer Part Number
IDTCSPT857
Description
2.5v Phase Locked Loop Differential 1 10 Sdram Clock Driver
Manufacturer
Integrated Device Technology
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDTCSPT857APA
Manufacturer:
IDT
Quantity:
531
Part Number:
IDTCSPT857DBVG
Manufacturer:
IDT
Quantity:
154
Part Number:
IDTCSPT857DNLG
Manufacturer:
IDT
Quantity:
1 164
Part Number:
IDTCSPT857DNLG
Manufacturer:
IDT
Quantity:
20 000
Part Number:
IDTCSPT857DPAGI
Manufacturer:
IDT
Quantity:
9
Part Number:
IDTCSPT857PA
Manufacturer:
EXAR
Quantity:
6 254
TIMING REQUIREMENTS
NOTES:
1.
2.
3.
4.
SWITCHING CHARACTERISTICS
NOTES:
1.
2.
3.
4.
5.
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
t
Symbol
JIT(HPER)
The PLL on the CSPT857 will meet all the above test parameters while supporting SSC synthesizers
t
JIT(PER)
t
t
V
t
t
JIT(CC)
SLR(O)
t
t
SSC
SSC
PLH (1)
PHL (1)
Symbol
t
SLR(I)
SK(O)
The PLL will track a spread spectrum clock input.
Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications.
Application clock frequency is the range over which timing specifications apply.
Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up.
t
f
Refers to transition of non-inverting output.
Static phase offset does not include jitter.
t() is measured with input clock slew rate t
The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
V
OX (5)
R,
3dB
()
OX
f
t
CLK
t
DC
F
t
L
is specified at the SDRAM clock input or test load.
Description
LOW to HIGH Level Propagation Delay Time
HIGH to LOW Level Propagation Delay Time
Jitter (period), see figure 6
Jitter (cycle-to-cycle), see figure 3
Half-Period Jitter, see figure 7
Output Clock Slew Rate (Single-Ended)
Input Clock Slew Rate
Static Phase Offset, see figure 4
Output Skew, see figure 5
Output Rise and Fall Times (20% to 80%)
Output Differential Voltage
Modulation Frequency
Clock Input Frequency Deviation
PLL Loop Bandwidth
Parameter
Operating Clock Frequency
Application Clock Frequency
Input Clock Duty Cycle
Stabilization Time
(4)
(1,2)
SLR
(1,3)
(2,3)
(
I
) = 2V/ns and an input differential voltage V
Test mode, CLK to any output
Test mode, CLK to any output
Load: 120 / 14pF
Differential outputs are terminated
Test Conditions
66MHz
100/ 133/ 167/ 200 MHz
66MHz
100/ 133/ 167/ 200 MHz
66MHz
100/ 133/ 167/ 200 MHz
100/ 133/ 167/ 200 MHz (20% to 80%)
66/ 100/ 133/ 167/ 200 MHz
with 120



6
ID
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
of 1.75V.
(4)
with the following parameters:
V
– 180
– 160
– 100
– 100
Min. Typ.
– 0.2
– 90
– 75
– 75
DDQ
650

30
1
0
1
/2
CSPT857
Min.

60
60
40
4.5
4.5


5
(1)
V
+ 0.2 – 0.15
Max.
DDQ
180
160
100
100
900
-0.5

75
75
90
75
50
2
4
/2 V
– 180
– 160
– 100
Min. Typ.
– 90
– 75
– 75
– 50
DDQ
650

30
1
1
0
/2
Max.
200
200
100
60
CSPT857A
4.5
4.5


5
(1)
V
+ 0.15
Max.
DDQ
-0.5
180
160
100
900

90
75
75
50
75
50
2
4
/2
MHz
MHz
Unit
s
%
MHz
Unit
V/ns
V/ns
KHz
%
ns
ns
ps
ps
ps
ps
ps
ps
V

Related parts for IDTCSPT857