MD1213 Supertex, Inc., MD1213 Datasheet - Page 6

• Manufacturer Part Number: MD1213
• Description: High Speed Dual MOSFET Driver
• Manufacturer: Supertex, Inc.

Application Information
For proper operation of the MD1213, low inductance bypass
capacitors should be used on the various supply pins. The
GND input pin should be connected to the digital ground.
The INA, INB, and OE pins should be connected to their
logic source with a swing of GND to logic level high, which is
1.2V to 5.0V. Good trace practices should be followed corre-
sponding to the desired operating speed. The internal circuit-
ry of the MD1213 is capable of operating up to 100MHz, with
the primary speed limitation being the loading effects of the
load capacitance. Because of this speed and the high tran-
sient currents that result with capacitive loads, the bypass
capacitors should be as close to the chip pins as possible.
Unless the load specifi cally requires bipolar drive, the V
V
connections directly to a ground plane. If these voltages are
not zero, then they need bypass capacitors in a manner sim-
ilar to the positive power supplies. The power connections
V
ground plane with short leads and decoupling components to
prevent resonance in the power leads. A common capacitor
and voltage source may be used for these two pins, which
should always have the same DC voltage applied. For ap-
plications sensitive to jitter and noise, separate decoupling
networks may be used for V
Pin Description
Note: 1.Thermal Pad and Pin#5 (V
SS2
DD1
Pin #
10
11
12
1
2
3
4
5
6
7
8
9
, and V
and V
2. Index Pad and Thermal Pad are connected internally
Name Description
OUT
OUT
DD2
GND
V
V
V
V
IN
OE
L
IN
V
V
DD2
DD1
SS1
SS2
pins should have low inductance feed-through
L
H
B
should have a ceramic bypass capacitor to the
A
B
A
Logic input. Controls OUT
logic low will cause the output to swing to V
Supply voltage for N-channel output stage.
Logic input. Controls OUT
logic low will cause the output to swing to V
Logic input ground reference.
Low side analog circuit and level shifter supply voltage. Should be at the same potential as V
Low side gate drive supply voltage.
Output driver. Swings from V
series capacitor. When OE is low, the output is disabled. OUT
N-channel MOSFET.
Supply voltage for P-channel output stage.
Output driver. Swings from V
series capacitor. When OE is low, the output is disabled. OUT
P-channel MOSFET.
High side gate drive supply voltage.
High side analog circuit and level shifter supply voltage. Should be at the same potential as V
Output-enable logic input. When OE is high, (V
level high and low for IN
and IN
B
DD1
SS1
) must be connected externally.
and V
DD2
.
A
A
B
and IN
when OE is high. Input logic high will cause the output to swing to V
when OE is high. Input logic high will cause the output to swing to V
H
H
to V
to V
B
. When OE is low, OUT
L
L
. Intended to drive the gate of an external N-channel MOSFET via a
. Intended to drive the gate of an external P-channel MOSFET via a
SS1
,
6
H
H
The supplied voltages of V
logic levels. These two pins can draw fast transient currents
of up to 2.0A, so they should be provided with an appropri-
ate bypass capacitor located next to the chip pins. A ceramic
capacitor of up to 1.0µF may be appropriate, with a series
ferrite bead to prevent resonance in the power supply lead
coming to the capacitor. Pay particular attention to minimiz-
ing trace lengths and using suffi cient trace width to reduce
inductance. Surface mount components are highly recom-
mended. Since the output impedance of this driver is very
low, in some cases it may be desirable to add a small series
resistor in series with the output signal to obtain better wave-
form integrity at the load terminals.
This will of course reduce the output voltage slew rate at
the terminals of a capacitive load. Pay particular attention
to the parasitic coupling from the driver output to the input
signal terminals. This feedback may cause oscillations or
spurious waveform shapes on the edges of signal transi-
tions. Since the input operates with signals down to 1.2V,
even small coupled voltages may cause problems. Use of a
solid ground plane and good power and signal layout prac-
tices will prevent this problem. Be careful that the circulating
ground return current from a capacitive load cannot react
with common inductance to cause noise voltages in the in-
put logic circuitry.
.
.
OE
+ V
GND
)/2 sets the threshold transition between logic
A
is at V
A
B
will swing to V
will swing to V
H
and OUT
H
and V
B
is at V
H
L
turning off the external
turning off the external
L
determine the output
L
regardless of IN
MD1213
SS2
DD2
L
L
.
. Input
. Input
.
A