SC28L202 Philips Semiconductors, SC28L202 Datasheet - Page 17

• Manufacturer Part Number: SC28L202
• Description: Dual universal asynchronous receiver/transmitter DUART
• Manufacturer: Philips Semiconductors

Philips Semiconductors
followed by the programmed number of data bits, an optional parity
bit, and the programmed number of stop bits. The least significant
bit is sent first. Following the transmission of the stop bits, if a new
character is not available in the TxFIFO, the TxD output remains
High and the Tx Idle bit in the Status Register (SR) will be set to 1.
Transmission resumes and the Tx Idle bit is cleared when the CPU
loads a new character into the TxFIFO.
If the transmitter is disabled, it continues operating until the
character currently being transmitted is completely sent out. The
transmitter can be forced to send a continuous Low condition by
issuing a send break command. The transmitter can be reset
through a software command. If it is reset, operation ceases
immediately and the transmitter must be enabled through the
command register before resuming operation.
If CTS option of hardware flow control is enabled (MR2 [4] = 1), the
CTS input at I/O0 or I/O1 must be Low in order for the character to
be transmitted. The transmitter will check the state of the CTS input
at the beginning of each character transmitted. If it is found to be
High, the transmitter will delay the transmission of any following
characters until the CTS has returned to the low state. CTS going
high during the serialization of a character will not affect that
character.
It is an interesting point of the I/O system inputs being always active
that by enabling transmitter to be sensitive the I/O0 or I/O1 and then
controlling the I/O pin as an out put that one is able to control the
transmitter flow via software control of the I/O pin.
The transmitter can also control the RTSN outputs, I/O0 or I/O1 via
MR2 [5]. When this mode of operation is set (often referred to as the
RS–485 method) the meaning of the I/O0 B or I/O1 B signals is “all
bytes loaded to the transmitter’s FIFO have been transmitted
including the last stop bit(s). See the MR2(5) description for enabling
this automatic function.
Receiver Operation
Receiver
The receiver accepts serial data on the RxD pin, converts the serial
input to parallel format, checks for start bit, stop bit, parity bit (if any),
framing error or break condition, and presents the assembled
character and its status condition to the CPU via the RxFIFO. Three
status bits are FIFOed with each character received. The RxFIFO is
really 11 bits wide: eight data and 3 status. Unused FIFO bits for
character lengths less than 8 bits are set to zero.
It is important to note that in the asynchronous protocol the receiver
logic considers the entire message to be contained within the start
bit to the stop bit. It is not aware that a message may contain many
characters. The receiver returns to its idle mode at the end of each
stop bit! As described below it immediately begins to search for
another start bit, which is normally, of course, immediately
forthcoming.
1x and 16x mode, Receiver
The receiver operates in one of two modes: 1x and 16x. Of the two,
the 16x is more robust and the preferred mode. Although the 1x
mode may allow a faster data rate is does not provide for the
alignment of the receiver 1x data clock to that of the transmitter. This
strongly implies that the 1x clock of the remote transmitter is
available to the receiver; the two devices are physically close to
each other.
The 16x mode operates the receiver logic at a rate 16 times faster
than the 1x data rate. This allows for validation of the start bit length,
the validation of level changes at the receiver serial data input
(RxD), and the validation of the stop bit length. Of most importance
2000 Feb 10
Dual UART
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in the 16x mode is the ability of the receiver logic to align the phase
of the internally generated receiver 1x data clock to that of the
received start bit of the remote transmitter. This occurs with an
accuracy of less than 1/16 bit time.
Receiver
The receiver of the 28L202 is conditioned to receive data when
enabled through the command register. The receiver looks for a
High–to–Low (mark–to–space) transition of the start bit on the RxD
input pin. If a transition is detected, the state of the RxD pin is
sampled each 16X clock for 7–1/2 clock periods (16X clock mode)
or at the next rising edge of the bit time clock (1X clock mode). If
RxD is sampled high, (that is the start bit was low less than 7/16 to
valid start bit begins immediately. If RxD is still low, a valid start bit is
assumed and the receiver then continues to sample the input at
one–bit time intervals at the theoretical center of the bit. When the
proper number of data bits and parity bit (if used) have been
assembled, and one half–stop bit has been detected the receiver
loads the byte to the FIFO. The least significant bit is received first.
The data is then transferred to the Receive FIFO and the ISR
RxRDY bit in the SR is set to a 1. This condition can be
programmed to generate an interrupt at IRQN or I/O[4:5] for
channels A or B respectively. If the character length is less than 8
bits, the most significant unused bits in the RxFIFO are set to zero.
After the stop bit is detected, the receiver will immediately look for
the next start bit. However, if a non–zero character was received
with the stop bit at a zero level (framing error) and RxD remains Low
for at least another one half bit time after the stop bit was sampled,
then the receiver operates as if a new start bit had been detected. It
then continues assembling the next character.
The error conditions of parity error, framing error, and overrun error
(if any) are written to the SR at the received character boundary.
This is just before the RxRDY status bit is set.
A break condition is detected when RxD is Low for the entire
character including the parity bit, if used, and stop bit. When a break
is found a character consisting of all zeros will be loaded into the
RxFIFO, the received break bit in the SR and the “change of break”
bit in the ISR are set to 1 and the receiver ready is set in the SR.
The RxD input must return to high for two (2) clock edges of the
RxC1x clock for the receiver to recognize the end of the break
condition. At the end of the break condition the search for the next
start bit begins.
Two edges of the RxC1x clock will usually require a high time of one
RxC1x clock period or 3 RxC1x edges since the clock of the
controller is usually not synchronous to nor in phase with the RxC1x
clock.
Receiver Status Bits
There are five (5) status bits that are evaluated with each byte (or
character) received: received break, framing error, parity error,
overrun error, and change of break. The first three are appended to
each byte and stored in the RxFIFO. The last two are not
necessarily related to the byte being received or a byte that is in the
RxFIFO. They are however developed by the receiver state
machine.
The ”received break” will always be associated with a zero byte in
the RxFIFO. It means that zero character was a break character and
not a zero data byte. The reception of a break condition will always
set the ”change of break” (see below) status bit in the Interrupt
Status Register (ISR).
bit time) the start bit is judged invalid and the search for another
Objective specification
SC28L202