SC2453 Semtech Corporation, SC2453 Datasheet - Page 10

• Manufacturer Part Number: SC2453
• Description: High Performance Quad Output Switching Regulator
• Manufacturer: Semtech Corporation

DUAL LDO CONTROLLERS
The SC2453 provides positive and negative adjustable
linear regulator controllers. The positive linear regulator
uses a PNP transistor to regulate output voltage. This is
set by a voltage divider connected from the output to FB
to AGND. Referring to the front page Application Circuit,
select R8 in the 5K
the following equation:
The negative linear regulator uses a NPN transistor to
regulate output voltage. This is set by a voltage divider
connected from the output to FB to a positive reference.
Referring to the front page Application Circuit, select R16
in the 5K
lowing equation:
where V
LAYOUT GUIDELINES
Careful attention to layout requirements are necessary
for successful implementation of the SC2453 PWM con-
troller. High switching current is present in the applica-
tion and their effect on ground plane voltage differen-
tials must be understood and minimized.
1). The high power parts of the circuit should be laid out
first. A ground plane should be used. The number and
position of ground plane interruptions should be such as
to not unnecessarily compromise ground plane integrity.
Isolated or semi-isolated areas of the ground plane may
be deliberately introduced to constrain ground currents
to particular areas, such as the input capacitor or the
bottom FET ground.
2). The loop formed by the Input Capacitor(s) (Cin), the
Top FET (Q
small as possible. This loop contains all the high current,
fast transition switching. Connections should be as wide
R
R
POWER MANAGEMENT
Applications Information (Cont.)
12
7
2002 Semtech Corp.
R
R
8
16
REF
V
0
OUT
V
V
5 .
T
is the positive voltage reference.
OUT
REF
) and the Bottom FET (Q
to 20K
1
range. Calculate R12 with the fol-
to 20K
range. Calculate R7 with
B
) must be kept as
10
and as short as possible to minimize loop inductance.
Minimizing this loop area will a) reduce EMI, b) lower
ground injection currents, resulting in electrically “cleaner”
grounds for the rest of the system and c) minimize source
ringing, resulting in more reliable gate switching signals.
3). The connection between the junction of Q
the output inductor should be a wide trace or copper
region. It should be as short as practical. Since this con-
nection has fast voltage transitions, keeping this con-
nection short will minimize EMI. Also keep the Phase con-
nection to the IC short. The top FET gate charge currents
flow in this trace.
4) The Output Capacitor(s) (Cout) should be located as
close to the load as possible. Fast transient load cur-
rents are supplied by Cout only and connections between
Cout and the load must be short, wide copper areas to
minimize inductance and resistance.
5) The SC2453 is best placed over a quiet ground plane
area. Avoid pulse currents in the Cin, Q
in this area. GND should be returned to the ground plane
close to the package and close to the ground side of
(one of) the output capacitor(s). If this is not possible,
the GND pin may be connected to the ground path be-
tween the Output Capacitor(s) and the Cin, Q1, Q2 loop.
Under no circumstances should GND be returned to a
ground inside the Cin, Q1, Q2 loop.
6) A separate analog ground plane connects to the
SC2453 AGND pin. All analog grounding paths including
decoupling capacitors, feedback resistors, compensation
components, and current-limit setting resistors should
be connected to this plane.
7) Ideally, the grounds for the two LDO sections should
be returned to the ground side of (one of) the output
capacitor(s).
PRELIMINARY
T
, Q
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SC2453
B
loop flowing
T
, Q
B
and