STA323W ST Microelectronics, STA323W Datasheet - Page 21

• Manufacturer Part Number: STA323W
• Description: 2.1 High Efficiency Digital Audio System
• Manufacturer: ST Microelectronics

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D a t a S h e e t
7.7.3 Binary Clock Loss Detection Enable
Detects loss of input MCLK in binary mode and will output 50% duty cycle to prevent audible artifacts when
input clocking is lost.
7.7.4 Auto-EAPD on Clock Loss Enable
When ECLE is active, it issues a power device power down signal (EAPD) on clock loss detection.
7.7.5 External Amplifier Power Down
EAPD is used to actively power down a connected DDX
1 at start-up to enable the DDX
7.8 VOLUME CONTROL
7.8.1 Master Controls
7.8.1.1Master Mute Register (Address 06h)
7.8.1.2Master Volume Register (Address 07h)
Note : Value of volume derived from MVOL is dependent on AMV AutoMode Volume settings.
7.8.2 Channel Controls
7.8.2.1Channel 1 Volume (Address 08h)
BIT
BIT
BIT
5
7
7
C1V7
MV7
4
D7
D7
D7
1
0
U
. c o m
R/W
R/W
R/W
R/W
R/W
R/W
D6
MV6
C1V6
D6
D6
1
1
RST
RST
RST
1
0
0
D5
MV5
C1V5
D5
®
D5
1
NAME
NAME
NAME
EAPD
BCLE
ECLE
1
power device for normal operation.
D4
Binary Output Mode Clock Loss Detection Enable
0 – Disabled
1 – Enabled
Auto EAPD on Clock Loss
0 – Disabled
1 – Enabled
External Amplifier Power Down:
0 – External Power Stage Power Down Active
1 – Normal Operation
MV4
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C1V4
D4
1
D4
0
D3
MV3
®
D3
C1V3
1
D3
Power device. This register has to be written to
0
D2
DESCRIPTION
DESCRIPTION
DESCRIPTION
MV2
D2
C1V2
1
D2
0
D1
MV1
C1V1
D1
1
D1
0
MMUTE
D0
STA323W
0
C1V0
MV0
D0
D0
1
0
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