STIR4200 SigmaTel, STIR4200 Datasheet - Page 18

• Manufacturer Part Number: STIR4200
• Description: USB / IrDA Bridge Controller
• Manufacturer: SigmaTel

STIr4200
USB/IrDA Bridge Controller
18
FIFO Count Register (LSB)
Default State
FIFO Count Register (MSB)
Default State
DPLL Tune Register
Default State
Bit Number Bit Mnemonic Access
Bit Number Bit Mnemonic Access
Bit Number Bit Mnemonic Access
7-0
7-5
4-0
7-2
1-0
6.1.6.
6.1.7.
FFCNT(12:8)
DPCNT(5: 0)
LONGP(1: 0)
FFCNT(7:0)
Reserved
FIFO Count Registers (LSB,MSB)
Offset 6&7
6.1.6.1.
Offset 6
6.1.6.2.
Offset 7
DPLL Tune Register
Offset 8
7
0
R/W
R/W
RO
RO
RO
7
0
7
0
FIFO Count LSB
FIFO Count MSB
6
1
When combined with the FIFO Count Registers (MSB), indicates the number
of bytes in the FIFO.
When combined with the FIFO Count Registers (LSB), indicates the number
of bytes in the FIFO.
Sets the sensitivity of the receiver’s digital PLL. This bit should be used for
chip debug purposes only. This register setting only affects FIR mode. The
default setting is proper for normal operation.
Sets the sensitivity of the pulse detector of the receiver. These bits should be
used for chip debug purposes only.
Reserved
Table 20. DPLL Tune Register
Table 19. FIFO Count MSB
Table 18. FIFO Count LSB
6
0
6
0
5
DPCNT(5: 0)
0
5
0
5
0
4
1
4
0
FFCNT(7: 0)
4
0
Write as zeros.
Function
Function
Function
3
0
3
0
3
0
FFCNT(12: 8)
2
0
2
0
2
0
3-4200-D1-2.0-0403
1
1
LONGP(1: 0)
1
0
1
0
0
0
0
0
0
0