ST14C02C ST Microelectronics, ST14C02C Datasheet - Page 5

• Manufacturer Part Number: ST14C02C
• Description: Memory Card IC 2 Kbit 256 x 8 Serial I2C Bus EEPROM
• Manufacturer: ST Microelectronics

period the receiver pulls the SDA bus low to ac-
knowledge the receipt of the 8 data bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transi-
tion, and the data must change only when the SCL
line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
8 bits to the SDA bus line (with the most significant
bit first). These bits represent the Device Select
Code (7 bits) and a RW bit.
The seven most significant bits of the Device Se-
lect Code are the Device Type Identifier, according
to the I
the seven bits are fixed at 1010000b (A0h), as
shown in Table 4.
The 8
set to ‘1’ for read and ‘0’ for write operations. If a
match occurs on the Device Select Code, the cor-
responding memory gives an acknowledgment on
the SDA bus during the 9
Write Operations
The Multibyte Write mode is selected when the
MODE pin is at V
selected when MODE pin is at V
may be driven dynamically to CMOS input levels.
Figure 6. Write Mode Sequences
th
2
bit is the read or write bit (RW). This bit is
C bus definition. For the memory device,
BYTE WRITE
PAGE WRITE
IH
, and the Page Write mode is
th
bit time.
IL
. The MODE pin
DEV SEL
DEV SEL
ACK
DATA IN N
R/W
R/W
ACK
ACK
BYTE ADDR
BYTE ADDR
ACK
Following a START condition, the master sends a
Device Select Code with the RW bit reset to ‘0’.
The memory device acknowledges this, and waits
for a byte address. The 8-bit byte address allows
access within a 256-byte memory address-space.
After receipt of the byte address, the device again
responds with an acknowledge bit.
Byte Write
In the Byte Write mode, the master sends one data
byte, which is acknowledged by the memory, as
shown in Figure 6. The master then terminates the
transfer by generating a STOP condition. The
Write mode is independent of the state of the
MODE pin, as shown in Table 5, which could be
left floating if only this mode is to be used. Howev-
er this is not a recommended operating mode, as
this pin has to be connected to either V
minimize the stand-by current.
Multibyte Write
For the Multibyte Write mode, the MODE pin must
be held at V
Write mode can be started from any address in the
memory. The master sends one, two, three or four
bytes of data, which are each acknowledged by
the memory. The transfer is terminated by the
master generating a STOP condition. The maxi-
mum duration of the write cycle is t
shown in Table 8), except when bytes span across
two rows. (That is, when they have different values
for the 6 most significant address bits, A7-A2). The
programming time is then doubled to a maximum
of 20 ms. Writing more than four bytes in the Multi-
ACK
ACK
IH,
DATA IN 1
DATA IN
as shown in Table 5. The Multibyte
ACK
ACK
DATA IN 2
AI01941
W
ST14C02C
=10 ms (as
IH
or V
IL
5/12
to