ST7565V Sitronix Technology, ST7565V Datasheet - Page 21

• Manufacturer Part Number: ST7565V
• Description: 65 x 132 Dot Matrix LCD Controller/Driver
• Manufacturer: Sitronix Technology

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ST7565V
Ver 1.5b
Pin Name
TEST0 ~ 6
/HPM
/DOF
SEL3
SEL2
SEL1
CLS
M/S
IRS
CL
FR
I/O
I/O
O
O
I
I
I
I
I
I
Terminal to select whether or enable or disable the display clock internal oscillator
circuit.
CLS = “H” : used Internal oscillator circuit .
CLS = “L” : used external clock input .(internal oscillator is disable)
When CLS = “L”, input the display clock through the CL terminal.
This terminal selects the master/slave operation for the ST7565V Series chips.
Master operation outputs the timing signals that are required for the LCD display, while slave
operation input the timing signals required for the liquid crystal display,
Synchronizing the
M/S = “H” Master operation
M/S = “L” Slave operation
This is the display clock input terminal
The following is true depending on the M/S and CLS status.
This is the liquid crystal alternating current signal terminal.
This is the LCD blanking control terminal.
This terminal selects the resistors for the V5 voltage level adjustment.
IRS = “H”: Use the internal resistors
IRS = “L”: Do not use the internal resistors. The V5 voltage level is
regulated by an external resistive voltage divider attached to the VR terminal
This is the power control terminal for the power supply circuit for liquid crystal drive.
/HPM = “H”: Normal mode
/HPM = “L”: High power mode
These pins are DUTY selection.
These are terminals for IC testing.
They are set to open.
M/S CLS
“H”
M/S
“L”
“H”
SEL 3 , 2 , 1
“L”
1, X , X
0 , 0 , 0
0 , 0 , 1
0 , 1 , 0
0 , 1 , 1
1 , 0 , 0
“H”
“H”
“L”
“L”
CLS
“H”
“H”
“L”
“L”
Oscillator
Disabled
Disabled
Disabled
Enabled
Circuit
Output
Input
Input
Input
CL
liquid crystal display system.
DUTY
1/65
1/49
1/33
1/55
1/53
Disabled
Disabled
-----
Enabled
Enabled
Supply
Circuit
Power
Output
Input
Input
Input
21/72
CL
1/9 or 1/7
1/8 or 1/6
1/6 or 1/5
1/8 or 1/6
1/8 or 1/6
Function
BIAS
-----
Output
Output
Input
Input
FR
Output
Output
Input
Input
DOF
No. of Pins
2009/09/14
1
1
1
1
1
1
1
3
6