MACH230-10 Lattice, MACH230-10 Datasheet
MACH230-10
Related parts for MACH230-10
MACH230-10 Summary of contents
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... FINAL MACH230-10/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 84 Pins 128 Macrocells Commercial Industrial PD 100 MHz f CNT 70 Inputs GENERAL DESCRIPTION The MACH230 is a member of the high-performance EE CMOS MACH 2 device family. This device has ap- proximately twelve times the logic macrocell capability of the popular PAL22V10 without loss of speed ...
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I/O 0 – I/O 7 (Block A) I/O 8 – I/O 15 (Block B) 8 I/O Cells Macrocells Macrocells Macrocells AND Logic Array and Logic Allocator AND Logic ...
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... Note: Pin-compatible with MACH130, MACH131, MACH231, and MACH435. PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V = Supply Voltage CC 84 PLCC MACH230-10/15/20 74 GND I ...
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... The Valid Combinations table lists configurations planned to be supported in volume for this device. Con- sult your local sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. MACH230-10/15/20 (Com’l) OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS C = Commercial ( +70 C) ...
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... The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availabil- ity of specific valid combinations and to check on newly released combinations. MACH230-18/24 (Ind) OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS I = Industrial (– +85 C) ...
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... The two product terms that are available are common to all I/O cells in a PAL block. These choices make it possible to use the macrocell as an output, an input, a bidirectional pin three-state output for use in driving a bus. MACH230-10/15/20 Table 2. Logic Allocation Macrocell Available Buried ...
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... Matrix Figure 1. MACH230 PAL Block MACH230-10/15/20 Output Enable Output Enable Asynchronous Reset Asynchronous Preset I/O Cell Output Macro M Cell 0 Buried Macro M Cell 1 I/O Cell Output M Macro 2 Cell Buried Macro M Cell ...
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... 0 Max (Note 3) OUT Outputs Open ( 5 MHz (Note 4) and I (or I and OZL IH OZH MACH230-10 (Com’ + +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –10 10 –10 –30 –130 = 0 mA) 235 OUT ...
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... Output Latch t Setup Time from Input, I/O, or Feedback Through SLL Transparent Input Latch to Output Latch Gate Test Conditions MHz OUT ) CNT MACH230-10 (Com’l) Typ Unit -10 Min Max Unit 10 ns D-type 6.5 ns T-type 7 ...
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... APR t Input, I/O, or Feedback to Output Enable EA t Input, I/O, or Feedback to Output Disable ER Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 10 MACH230-10 (Com’l) -10 Min Max Unit ...
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... OUT (Note 0 Max (Note 3) OUT MHz CC A (Note 4) and I (or I and OZL IH OZH MACH230-15/20 (Com’ + +4. +5.25 V Min Typ Max Unit 2.4 V 0.5 V 2 – –10 A – ...
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... MHz OUT D-type T-type LOW HIGH D-type 1/( T-type D-type ) CNT T-type 1/( D-type T-type LOW HIGH 1/( WICL WICH MACH230-15/20 (Com’l) Typ Unit -15 -20 Min Max Min Max Unit ...
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... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. See Switching Test Circuit for test conditions. 3. Parameters measured with 32 outputs switching. Min MACH230-15/20 (Com’l) -15 -20 Max Min Max ...
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... VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VCC = MHz (Note 4) MACH230-18/24 (Ind – + with ...
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... D-type 40 1/( T-type 38 D-type 53 ) CNT T-type 44 66.5 1/( 7.5 2.5 3.5 D-type 18 T-type 19.5 LOW 7.5 HIGH 7.5 1/(tWICL + tWICH ) 66.5 2.5 3.5 14.5 19.5 7.5 MACH230-18/24 (Ind) Typ Unit -18 -24 Max Min Max Unit 14 MHz 30.5 MHz 38 MHz 34.5 MHz 50 MHz 16 ns ...
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... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. See Switching Test Circuit for test conditions. 3. Parameters measured with 32 outputs switching. 16 Min MACH230-18/24 (Ind) -18 -24 Max Min Max Unit ...
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... Output, LOW I (mA –3 –2 –1 –25 –50 –75 –100 –125 –150 Output, HIGH I (mA –2 – –20 –40 –60 –80 –100 Input MACH230-10/15/ 1.0 14132I (V) OH 14132I 14132I-6 17 ...
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... The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register Frequency (MHz) MACH230-10/15/20 MACH230 60 70 14132I-7 ...
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... Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air MACH230-10/15/20 Typ PLCC Units 5 C/W ...
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... Gate t WL 14132I- Registered Input t HIR Input V T Register Clock t ICO V T Output Register Clock 14132I-13 MACH230-10/15/ 14132I PDL Latched Output (MACH 2, 3, and GWS 14132I-12 Gate Width (MACH 2, 3, and ...
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... Input pulse amplitude 3 Input rise and fall times 2 ns–4 ns typical SIL HIL Latched Input (MACH 2 and 4) t IGOL Latched Input and Output (MACH 2, 3, and 4) MACH230-10/15/ IGO V T 14132I-15 t PDLL SLL ...
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... Gate t WICL 14132I-17 Input, I/ Feedback Registered V T Output t ARR Clock V T 14132I- Outputs + V OL Output Disable/Enable MACH230-10/15/20 t WIGL Input Latch Gate Width (MACH 2 and 4) t APW Asynchronous Preset 0. 0.5V 14132I- 14132I- APR ...
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... Apply Output Commercial 300 390 5 pF MACH230-10/15/20 OUTPUTS Will be Steady Will be Changing from Will be Changing from Changing, State Unknown Center Line is High- Impedance “Off” State KS000010-PAL Test Point 14132I-22 Measured ...
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... All frequencies except f MAX other measured AC parameters. f ured directly. ” (SECOND CHIP MACH230-10/15/ type is the mini- MAX + t ). Usually, this minimum feedback.” MAX . Because this involves no MAXIR + the sum of SIR HIR + t ). The clock widths are nor- ...
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... Min Pattern Data Retention Time Max Reprogramming Cycles bipolar parts result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Min Units 10 Years 20 Years 100 Cycles MACH230-10/15/20 Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions 25 ...
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... INPUT/OUTPUT EQUIVALENT SCHEMATICS ESD Protection Input 100 k Preload Feedback Circuitry Input I/O MACH230-10/15/20 CC 100 14132I-24 ...
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... Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met Power-Up Reset Waveform MACH230-10/15/20 can rise to its steady state, two CC rise must be monotonic. Max 10 See Switching Characteristics V CC ...
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... All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support Preload Off Mode Figure 2. Preload/Reset Conflict Set Reset Figure 3. Combinatorial Latch MACH230-10/15/20 Preloaded HIGH Preloaded HIGH 14132I-26 14132I-27 ...
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... REF .032 TOP VIEW *For reference only. BSC is an ANSI standard for Basic Space Centering. .062 .083 .042 .056 .007 .013 .090 .130 .165 .180 SIDE VIEW MACH230-10/15/20 1.090 1.130 1.000 REF .013 .021 SEATING PLANE 16-038-SQ PL 084 DF79 8-1- ...