MAC7100CVF Motorola, MAC7100CVF Datasheet - Page 17

• Manufacturer Part Number: MAC7100CVF
• Description: MAC7100 Microcontroller Family Hardware Specifications
• Manufacturer: Motorola

Electrical Characteristics
3.8.3
1
2
3
4
5
3.8.4
The time-out Table 19 shows the delay for the crystal monitor to trigger when the clock stops, either at the high
or at the low level. The corresponding clock period with an ideal 50% duty cycle is twice this time-out value.
3.8.5
The timing for the clock quality check is derived from the oscillator and the VCO frequency range in
Table 18. These numbers define the upper time limit for the individual check windows to complete.
17
Num C
J10
J12
J13
J14
J15
J16
J11
J1
J2
J3
J4
J5
J6
J7
J8
J9
V
Percentage deviation from target frequency
PLL stabilization delay is highly dependent on operational requirement and external component values (for
example, crystal and XFC filter component values). Notes 4 and 5 show component values for a typical
configurations. Appropriate XFC filter values should be chosen based on operational requirement of system.
f
f
REF
REF
DD
PLL at 2.5 V.
P Self Clock Mode frequency
D VCO locking range
D Lock Detector transition from Acquisition to Tracking mode
D Lock Detection
D Un-Lock Detection
D Lock Detector transition from Tracking to Acquisition mode
C PLLON Total Stabilization delay (Auto Mode)
D PLLON Acquisition mode stabilization delay
D PLLON Tracking mode stabilization delay
D Charge pump current acquisition mode
D Charge pump current tracking mode
D Jitter fit VCO loop gain parameter
D Jitter fit VCO loop frequency parameter
C Jitter fit parameter 1
C Jitter fit parameter 2
= 4 MHz, f
= 4 MHz, f
PLL reference frequency, crystal oscillator range
PLL Characteristics
Crystal Monitor Time-out
Clock Quality Checker
Clock Check Windows
SYS
SYS
Timeout Window
Check Window
= 25 MHz (REFDV = 0x03, SYNR = 0x01), C
= 8 MHz (REFDV = 0x00, SYNR = 0x01), C
Min
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
6
MAC7100 Microcontroller Family Hardware Specifications
Table 20. CRG Maximum Clock Quality Check Timings
Freescale Semiconductor, Inc.
For More Information On This Product,
Rating
Table 19. Crystal Monitor Time-Outs
Table 18. PLL Characteristics
Go to: www.freescale.com
Typ
10
3
9.1 to 20.0
0.46 to 1.0
3
3
Value
1
S
S
= 33 nF, C
Max
18.5
Symbol
= 4.7 nF, C
|∆
|∆
|∆
f
f
|∆
| i
| i
f
t
t
SCM
VCO
REF
stab
Lock
acq
K
t
f
ch
ch
j
j
unl
unt
al
trk
1
1
2
1
|
|
|
|
|
|
P
P
= 3.3 nF, R
Min
0.5
0.5
= 470 pF, R
—
—
—
—
—
—
—
—
—
1
8
3
0
6
Unit
ms
s
Unit
S
–100
µs
0.5
0.3
0.2
38.5
Typ
3.5
—
—
—
—
—
—
—
60
—
—
= 2.7 K
S
4
5
5
= 10 K
Ω
Ω
.
Max
TBD
TBD
5.5
1.5
2.5
3
1
2
16
40
MOTOROLA
—
—
—
—
4
8
.
5
4
4
MHz/V
MHz
MHz
MHz
MHz
Unit
%
%
%
%
%
%
ms
ms
ms
µA
µA
2
2
2
2
4
4