SM5956A NPC, SM5956A Datasheet
SM5956A
Related parts for SM5956A
SM5956A Summary of contents
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... OVERVIEW The SM5956A is a digital audio signal, asynchronous sample rate converter LSI. It reads 6-channel 16/20/24- bit word length input data, and 16/20/24-bit word length output data. It also features a built-in digital deempha- sis filter, direct muting and digital audio interface output. FEATURES ...
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... Applications Sample rate conversion between digital audio I equipment (AV amplifiers, CD-R/RW, MD, DVC etc.) Sample rate conversion in commercial record- I ing/editing equipment SM5956A Converter Performance Internal data word length: 20 bits I Deemphasis filter characteristics (IIR filter) I • Gain deviation from ideal filter characteristic: ± 0.03dB ...
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... DIC 7 IWL0 8 IWL1 9 IMOD0 10 IMOD1 11 TEST4 12 VSS 13 VDD SM5956A LRCI BCKI Input data interface Sequencer block Interpolation operation Output data operation Conversion rate detector Output timing operation MCU interface Digital audio interface Output data interface Through, mute, and slave mode control ...
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... SCK 43 VSS 44 SCKSLN 45 ERROR 46 RSTN 47 SELFN 48 VSS input output input with pull-down Schmitt input, − = supply SM5956A 1 I/O Function I Deemphasis select I Deemphasis frequency select 0 I Deemphasis frequency select 1 Is MCU interface clock input Is MCU interface data input Is MCU interface latch enable input ...
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... Supply voltage Input voltage Output voltage Storage temperature Power dissipation Note. Ratings also apply when power is turned ON/OFF. RECOMMENDED OPERATING CONDITIONS V = 0V, VDD pins = V SS Parameter Supply voltage Operating temperature SM5956A DD Symbol Rating − 0 − 0 − 0 − 125 ...
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... Although input/output pins in input mode can accept 5.5V as the maximum input voltage, the maximum output voltage in output mode is VDD level forbidden to add more voltage than VDD to output mode bidirectional pins (external pull-up or other means). SM5956A Pin Symbol ...
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... Parameter Clock pulse cycle time HIGH-level clock pulsewidth LOW-level clock pulsewidth Clock pulse duty SCK Reset input (RSTN input) Parameter RSTN pulsewidth Note output-system clock (SCK input) cycle time CY RSTN SM5956A Symbol Condition SCKSLN = SCKSLN = H SCKSLN = L t CWH SCKSLN = H SCKSLN = L t ...
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... LRCI cycle time BCKI pulse cycle time BCKI HIGH-level pulsewidth BCKI LOW-level pulsewidth DI* setup time DI* hold time Last BCKI rising edge → LRCI edge LRCI edge → first BCKI rising edge LRCI BCKI DI* SM5956A Symbol Condition t LICY t BICY t BICWH t BICWL t DIS ...
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... LRCO cycle time BCKO pulse cycle time BCKO HIGH-level pulsewidth BCKO LOW-level pulsewidth Last BCKO rising edge → LRCO edge LRCO edge → first BCKO rising edge DO* output delay LRCO BCKO DO* SM5956A Symbol Condition t LOCY SCKSLN = L 312.5 t BOCY SCKSLN = H 416.6 SCKSLN = L ...
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... BCKO pulse cycle time BCKO HIGH-level pulsewidth BCKO LOW-level pulsewidth BCKO output delay LRCO output delay DO* output delay Note output-system clock (SCK input) cycle time CY SCK LRCO BCKO DO* SM5956A Symbol Condition SCKSLN = L t LOCY SCKSLN = H SCKSLN = L t LOCWH SCKSLN = H SCKSLN = L t LOCWL ...
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... MDT setup time MDT hold time MLE LOW-level pulsewidth MLE setup time MLE hold time Rise time Fall time Note output-system clock (SCK input) cycle time CY MDT MCK MLE MCK MDT MLE SM5956A Symbol Condition MCY MCWH MCWL MDS t ...
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... Continuous bit clock (64fso/48fso) Format IIS MSB-first left-justified MSB-first right-justified MSB-first right-justified Output word length I • 16/20/24-bit Output word length 16 bits 20 bits 24 bits 24 bits SM5956A IMOD1 IMOD0 IWL1 OMOD1 OMOD0 ...
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... In master mode, the LRCO and BCKO signals are derived from this clock input by frequency division. This clock is also used as the system clock by the internal processing circuits. SCKSLN L H SM5956A Function Mode Description LRCO, BCKO are derived by frequency division of Master the SCK input clock ...
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... HIGH-level when the observed counts does not agree with the expected counts. Therefore it needs some time for ERROR to reflect a condition of the clock (see table below). In the case of SELFN = L, the same time is required to change H → L. Output frequency [kHz] 32 44.1 48 SM5956A The ERROR by LRCI, BCKI stopping min [ms] max [ms] 6.0 8.0 4.3 5 ...
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... Audio data is output from the next output word. Other mute operations Direct mute is also applied during reset input cycles. RSTN L 0 data is output from the next output word. H Processor data is output after the 8th output word after RSTN goes HIGH. SM5956A Function Function Function SEIKO NPC CORPORATION —15 ...
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... MCU Interface (MDT, MCK, MLE pins) The SM5956A has a 3-wire serial MCU interface that is used to set the digital audio interface channel status data. Command format The commands from a microcontroller are input using the data input (MDT), bit clock (MCK), and load signal (MLE) inputs in bit serial format ...
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... DIA is sample rate converted, then a preamble is added and biphase mark encoded to form the output. In through mode, the DITO pin is forcibly tied LOW-level. When the SM5956A is operating in slave mode, the digital interface does not operate whenever the LRCO/BCKO are not operating as inputs. ...
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... Parity bit The parity bit is used to indicate when an odd number of errors occur due to interface problems. The SM5956A sets the parity bit the number of 1 bits in the other 27 data bits of the digital audio interface (excluding the preamble) is odd, and sets the parity bit the number of 1 bits is even, thereby insuring that the number of 1 bits in the 28-bit data is always even ...
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... Combined output theoretical S/N Output word length 16 bits 20 bits 24 bits Anti-aliasing filter characteristics 0 -20 -40 -60 -80 -100 -120 0 SM5956A Stopband attenuation > 98dB −98dB −122dB 20-bit output −146dB 24-bit output Input word length 16 bits 20 bits −92.3dB −94.0dB −94.0dB −96.0dB −94.1dB − ...
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... Deemphasis filter characteristics 0.0 -2.0 -4.0 -6.0 -8.0 -10.0 -12 -10 -20 -30 -40 -50 -60 -70 -80 -90 10 SM5956A FS0 FS1 100 1000 Frequency [Hz] Deemphasis filter frequency response 100 1000 Frequency [Hz] Deemphasis filter phase response 44.1kHz 48kHz 32kHz 10000 100000 32kHz 44 ...
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... A certain amount of time is required to calculate the sample rate conversion ratio in the conversion rate detec- tor. Assuming as a prerequisite that the SM5956A is supplied with a stable input-system sampling frequency (fsi: input on LRCI) and a stable output-system sampling frequency (fso: derived from the SCK clock), the time required after system reset to determine the sample rate conversion ratio with 16-bit precision is defi ...
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... Figure 4. 16-bit MSB-first left-justified (IMOD1 = L, IMOD0 = H, IWL1 = L, IWL0 = L) BCKI = 32fsi to 64fsi LRCI (fsi) BCKI (64fsi) DIA, DIB, DIC 1 2 Figure 5. 20-bit MSB-first left-justified (IMOD1 = L, IMOD0 = H, IWL1 = L, IWL0 = H) BCKI = 40fsi to 64fsi SM5956A Lch Lch ...
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... BCKI (64fsi) DIA, DIB, DIC 1 2 Figure 8. 20-bit IIS (IMOD1 = L, IMOD0 = L, IWL1 = L, IWL0 = H) BCKI = 64fsi only LRCI (fsi) BCKI (64fsi) DIA, DIB, DIC 1 2 Figure 9. 24-bit IIS (IMOD1 = L, IMOD0 = L, IWL1 = H, IWL0 = H) BCKI = 64fsi only SM5956A Lch Lch Lch 19 ...
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... Figure 13. 16-bit MSB-first left-justified (OMOD1 = L, OMOD0 = H, OWL1 = L, OWL0 = L) BCKO = 48fso (SCKSLN = H), 64fso (SCKSLN = L, the above) LRCO (fso) BCKO (64fso) DOA, DOB, DOC 1 2 Figure 14. 20-bit MSB-first left-justified (OMOD1 = L, OMOD0 = H, OWL1 = L, OWL0 = H) BCKO = 48fso (SCKSLN = H), 64fso (SCKSLN = L, the above) SM5956A Lch Lch 1 2 ...
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... Figure 17. 20-bit IIS (OMOD1 = L, OMOD0 = L OWL1 = L, OWL0 = H) BCKO = 48fso (SCKSLN = H), 64fso (SCKSLN = L, the above) LRCO (fso) BCKO (64fso) DOA, DOB, DOC 1 Figure 18. 24-bit IIS (OMOD1 = L, OMOD0 = L, OWL1 = H, OWL0 = H) BCKO = 48fso (SCKSLN = H), 64fso (SCKSLN = L, the above) SM5956A Lch 23 24 Lch Lch ...
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... SM5956AF OMOD0 OMOD1 THROUN TEST0 TEST1 SLAVEN TEST2 OWL0 TEST3 OWL1 TEST4 SCKSLN LRCI BCKI DIA 5V DEEMN IMOD0 IMOD1 SM5956AF TEST0 TEST1 TEST2 IWL0 TEST3 IWL1 TEST4 FS0 FS1 RMCK FSY SCK-SRC FL SR0-D3 MOST OS8104 5V /RD /WR PAR CP PAR SRC ASYNC PAD0 PAD1 SEIKO NPC CORPORATION — ...
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... Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. SM5956A SEIKO NPC CORPORATION 15-6, Nihombashi-kabutocho, Chuo-ku, ...