SM5902AF Nippon Precision Circuits Inc, SM5902AF Datasheet - Page 32

• Manufacturer Part Number: SM5902AF
• Description: compression and non compression type shock-proof memory controller
• Manufacturer: Nippon Precision Circuits Inc

Subframe parity
The parity bit is used to indicate the detection of an
odd number of bit errors. It is set to 1 if the number
of 1s in the digital audio interface 27-bit data is odd,
User bit data
User bit data is data specified by the user. The data
is output, after the Q data has been specified, in the
following sequence.
- Using Q data
Initially, Q
the DIT flag is set using the 86H command, and
then data is output from DIT according to the digital
audio interface format. Q
required as these are set internally by CRC calcula-
tion.
There are 2 Q data buffers; a data output buffer
and a data storage buffer. As a result, after all data
has been specified in the first data write, only that
data that has changed needs to be written during
the 2nd and subsequent data write operations.
Note that address 1001 is the write stop command
Audio channel status
The channel status are information bits transferred
to indicate the audio sample data length, preem-
phasis, sampling frequency, time code, source
1164
112
128
144
160
176
12
24
36
1
16
32
48
64
80
96
0
0
to Q
CTL0 CTL1 CTL2 CTL3
80
0
0
0
1
1
1
•
0
0
0
0
0
0
0
0
0
0
0
0
are set using the 87H command,
Q
Q
Q
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
•
96
1
2
2
0
0
0
0
•
0
2
0
0
0
0
0
0
0
0
0
0
0
81
to Q
3
0
0
0
0
•
0
3
0
0
0
0
0
0
0
0
0
0
0
96
L= 1
4
0
0
0
0
0
•
4
0
0
0
0
0
0
0
0
0
0
0
data are not
R= 1
5
0
0
0
0
0
5
0
0
0
0
0
0
0
0
0
0
0
•
SM5902AF
6
0
0
0
0
•
0
6
0
0
0
0
0
0
0
0
0
0
0
0
7
0
0
0
0
•
0
7
0
0
0
0
0
0
0
0
0
0
0
0
and is set to 0 if the number of 1s is even. The 27-
bit data plus parity bit form 28-bit data that always
has an even number of 1s.
and is, therefore, required after every data write
operation.
When space becomes available in the data output
buffer, QRDY is set to 1 (91H command status bit
S3) to indicate available space and then the con-
tents of the data storage buffer are transferred to
the data output buffer. After data is transferred, a
data write to address 1001 (write stop command)
resets the QRDY flag to 0.
The Q data buffer read access time for a complete
data cycle is approximately 13.3 ms.
number, destination code, and other information.
Seven bits comprising CP1, CP2, LBIT, and CTL0
to CTL3 can be set. All other bits are fixed.
8
0
0
0
0
0
8
1
0
0
0
0
0
0
0
0
0
0
0
•
9
0
0
0
0
•
0
9
0
0
0
0
0
0
0
0
0
0
0
0
10
10
0
0
0
0
•
0
0
0
0
0
0
0
0
0
0
0
0
0
NIPPON PRECISION CIRCUITS-32
11
11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
•
CP1
12
0
0
0
0
0
0
0
0
0
0
0
CP2
13
0
0
0
0
0
0
0
0
0
0
0
14
0
0
0
0
0
0
0
0
0
0
0
0
LBIT
15
0
0
0
0
0
0
0
0
0
0
0