SM5877 Nippon Precision Circuits Inc, SM5877 Datasheet - Page 13

• Manufacturer Part Number: SM5877
• Description: 3rd-order / 2-channel D/A Converter
• Manufacturer: Nippon Precision Circuits Inc

System Reset (RSTN)
The device should be reset in the following cases.
Audio Data Input (DI, BCKI, LRCI)
The digital audio data is input on DI in MSB-first, 2s-
complement, 16-bit serial format.
Serial data bits are read into the SIPO register (serial-
to-parallel converter register) on the rising edge of the
bit clock BCKI.
The arithmetic operation and output timing are inde-
pendent of the input timing. Accordingly, after a reset,
FUNCTIONAL DESCRIPTION
System Clock/Speed Switching (XTI, XTO, CKO, DS)
The system clock on XTI can be set to run at one of
two speeds, 384fs (normal speed) or 192fs (double-
speed), where fs is the input frequency on LRCI. The
speed for CD playback is set by the input level on
DS, as shown in table 1. The system clock should be
fixed at 16.9344 MHz.
Table 1. System clock select
XTI input clock
frequency
CD playback
XTI frequency
CKO output
clock frequency
Internal system
clock period
Internal reset
At power ON
When LRCI and/or the system clock XTI stop, or
other abnormalities occur.
Parameter
RSTN
LRCI
RO
LO
Symbol
(= 1/t
T
f
f
f
SYS
CO
XI
XI
XI
)
LOW
16.9344 MHz
at fs = 44.1
(normal
speed)
384fs
384fs
LOW
kHz
t
XI
1
DS
Figure 1. System reset timing
16.9344 MHz
at fs = 88.2
(double
speed)
HIGH
192fs
192fs
kHz
t
XI
2
SM5877AM
Outputs muted
Note that the input clock accuracy and signal-to-
noise ratio greatly influence the AC analog character-
istics. Accordingly, care should be taken to ensure
that the clock is free from jitter.
The system clock can be controlled by a crystal
oscillator comprising a crystal connected between
XTI and XTO and the built-in CMOS inverter. Alter-
natively, an external system clock can be input on
XTI. As the internal CMOS inverter has a feedback
resistor, the external clock can be AC coupled to
XTI. The system clock is output on CKO.
The device is reset by applying a LOW-level pulse on
RSTN. At system reset, the internal arithmetic opera-
tion and output timing counter are synchronized on
the next LRCI rising edge, as shown in figure 1.
as long as the clock frequency ratio between LRCI
and the system clock XTI is maintained, phase dif-
ferences between LRCI, BCKI and the system clock
XTI do not affect the functional operation. Also, any
jitter present on the data input clock does not appear
as output pulse jitter.
The bit clock frequency on BCKI should be between
32fs and 64fs.
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