VT1621M VIA, VT1621M Datasheet - Page 21

• Manufacturer Part Number: VT1621M
• Description: TV Encoder
• Manufacturer: VIA

Digital Video Interface
The VT1621 and the VT1621M can both be configured with
an 8-bit or 12-bit data bus. It accepts RGB 16-bit, RGB 15-
bit, RGB 24-bit or YCrCb 16-bit (CCIR 656) data format.
Each rising edge (or each rising and falling edge) of the XCLK
signal will latch data from the video source device.
multiplexed input data formats are shown in Figure 6. The
Pixel Data bus represents an 8 or 12-bit multiplexed data
stream, which contains either RGB or YCrCb formatted data.
In IDF settings 4, 5, 7, 8 and 9, the input data rate is 2X the
pixel clock frequency and each pair of P# values (for example,
P#A and P#B) will contain a complete pixel, encoded as
shown in Table 4. When IDF = 6, the input data rate is 3X the
pixel clock frequency and each triplet of P# values (for
example, P#A, P#B and P#C) will contain a complete pixel,
Revision 1.0 June 17, 2002
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Figure 6. Input Interface Protocol
The
- 16-
encoded as shown in Table 4. When the input is YCrCb, the
color-difference data will be transmitted at half the data rate of
the luminance data, with the sequence being set as Cb, Y, Cr,
Y. When IDF = 9 (YCrCb 8-bit mode), the H and V sync
signals can be embedded into the data stream. In this mode,
the embedded sync will follow the CCIR656 convention and
the first byte of the “video timing reference code” will be
assumed to occur when a Cb sample would occur if the video
stream is continuous.
8-bit multiplexed mode
− RGB 15-bit: 5-5-5 over two bytes
− RGB 16-bit: 5-6-5 over two bytes
− RGB 24-bit: 8-8-8 over three bytes
− YCrCb 16-bit: Cb, Y0, Cr, Y1
12-bit multiplexed mode
− RGB 24-bit: 8-8-8 over two words
VT1621 / VT1621M TV Encoder
Functional Descriptions